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參數(shù)資料
| 型號： | MPC8240EC |
| 廠商： | Motorola, Inc. |
| 英文描述： | Integrated Processor Hardware Specifications |
| 中文描述： | 綜合處理器硬件規(guī)格 |
| 文件頁數(shù)： | 36/52頁 |
| 文件大?。?/td> | 1027K |
| 代理商： | MPC8240EC |
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36
MPC8240 Integrated Processor Hardware Specifications
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
System Design Information
Figure 24. PLL Power Supply Filter Circuit
1.7.2
Power Supply Sizing
The power consumption numbers provided in Table 5 do not reflect power from the OV
DD
and GV
DD
power
supplies that are non-negligible for the MPC8240. In typical application measurements, the OV
DD
power
ranged from 200 to 600 mW and the GV
DD
power ranged from 300 to 900 mW. The ranges’ low-end power
numbers were results of the MPC8240 performing cache-resident integer operations at the slowest
frequency combination of 33:66:166 (PCI:Mem:CPU) MHz. The OV
DD
high-end range’s value resulted
from the MPC8240 performing continuous flushes of cache lines with alternating ones and zeros to PCI
memory. The GV
DD
high-end range’s value resulted from the MPC8240 operating at the fastest frequency
combination of 66:100:250 (PCI:Mem:CPU) MHz and performing continuous flushes of cache lines with
alternating ones and zeros on 64-bit boundaries to local memory.
1.7.3
Decoupling Recommendations
Due to its dynamic power management feature, large address and data buses, and high operating
frequencies, the MPC8240 can generate transient power surges and high frequency noise in its power
supply, especially while driving large capacitive loads. This noise must be prevented from reaching other
components in the MPC8240 system, and the MPC8240 itself requires a clean, tightly regulated source of
power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each
V
DD
, OV
DD
, GV
DD
, and LV
DD
pin of the MPC8240. It is also recommended that these decoupling capacitors
receive their power from separate V
DD
, OV
DD
, GV
DD
, and GND power planes in the PCB, utilizing short
traces to minimize inductance. These capacitors should have a value of 0.1 μF. Only ceramic SMT (surface
mount technology) capacitors should be used to minimize lead inductance, preferably 0508 or 0603,
oriented such that connections are made along the length of the part.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the V
DD
, OV
DD
, GV
DD
, and LV
DD
planes, to enable quick recharging of the smaller chip capacitors.
These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick
response time necessary. They should also be connected to the power and ground planes through two vias
to minimize inductance. Suggested bulk capacitors: 100–330 μF (AVX TPS tantalum or Sanyo OSCON).
1.7.4
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to OV
DD
. Unused active high inputs should be connected to
GND. All NC (no connect) signals must remain unconnected.
Power and ground connections must be made to all external V
DD
, OV
DD
, GV
DD
, LV
DD
, and GND pins of the
MPC8240.
The PCI_SYNC_OUT signal is intended to be routed halfway out to the PCI devices and then returned to
the PCI_SYNC_IN input of the MPC8240.
V
DD
AV
DD
10
2.2 μF
2.2 μF
GND
Low ESL Surface Mount Capacitors
F
Freescale Semiconductor, Inc.
n
.
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| MPC8241LVR266D | 功能描述:微處理器 - MPU INTEGRATED HOST PROC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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