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| 型號： | MPC8240EC |
| 廠商： | Motorola, Inc. |
| 英文描述： | Integrated Processor Hardware Specifications |
| 中文描述： | 綜合處理器硬件規(guī)格 |
| 文件頁數(shù)： | 6/52頁 |
| 文件大?。?/td> | 1027K |
| 代理商： | MPC8240EC |
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6
MPC8240 Integrated Processor Hardware Specifications
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Electrical and Thermal Characteristics
1.4.1.2
Recommended Operating Conditions
Table 2 provides the recommended operating conditions for the MPC8240.
Table 2. Recommended Operating Conditions
1
Characteristic
Symbol
Recommended
Value
Unit
Notes
Supply voltage
V
DD
2.5
±
5%
V
4, 6
Supply voltage for PCI and standard bus standards
OV
DD
3.3
±
0.3
V
6
Supply voltages for memory bus drivers
GV
DD
3.3
±
5%
V
8
PLL supply voltage—CPU core logic
AV
DD
2.5
±
5%
V
4, 6
PLL supply voltage—peripheral logic
AV
DD
2
2.5
±
5%
V
4, 7
DLL supply voltage
LAV
DD
2.5
±
5%
V
4, 7
PCI reference
LV
DD
5.0
±
5%
V
9, 10
3.3
±
0.3
V
9, 10
Input voltage
LV
input-tolerant signals
V
in
0 to 3.6 or 5.75
V
2, 3
All other inputs
0 to 3.6
V
5
Die-junction temperature
T
j
0 to 105
°C
Notes:
1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions
is not guaranteed.
2. These signals are designed to withstand LV
DD
+ 0.5 V DC when LV
DD
is connected to a 3.3- or 5.0-V DC power
supply.
3. LV
DD
input tolerant signals: PCI interface, PIC control, and OSC_IN signals.
4. See Section 1.9, “Ordering Information,” for details on a modified voltage (V
DD
) version device.
Cautions:
5. Input voltage (V
in
) must not be greater than the supply voltage (V
DD
/AV
DD
/AV
DD
2/LAV
DD
) by more than 2.5 V at all
times, including during power-on reset.
6. OV
DD
must not exceed V
DD
/AV
DD
/AV
DD
2/LAV
DD
by more than 1.8 V at any time, including during power-on reset.
This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
7. V
DD
/AV
DD
/AV
DD
2/LAV
DD
must not exceed OV
DD
by more than 0.6 V at any time, including during power-on reset.
This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
8. GV
DD
must not exceed V
DD
/AV
DD
/AV
DD
2/LAV
DD
by more than 1.8 V at any time, including during power-on reset.
This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
9. LV
DD
must not exceed V
DD
/AV
DD
/AV
DD
2/LAV
DD
by more than 5.4 V at any time, including during power-on reset.
This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
10.LV
DD
must not exceed OV
DD
by more than 3.6 V at any time, including during power-on reset. This limit may be
exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
F
Freescale Semiconductor, Inc.
n
.
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