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| 型號： | MPC8240EC |
| 廠商： | Motorola, Inc. |
| 英文描述： | Integrated Processor Hardware Specifications |
| 中文描述： | 綜合處理器硬件規(guī)格 |
| 文件頁數(shù)： | 35/52頁 |
| 文件大?。?/td> | 1027K |
| 代理商： | MPC8240EC |
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MOTOROLA
MPC8240 Integrated Processor Hardware Specifications
For More Information On This Product,
Go to: www.freescale.com
35
System Design Information
1.7
System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8240.
1.7.1
PLL Power Supply Filtering
The AV
DD
, AV
DD
2, and LAV
DD
power signals on the MPC8240 provide power to the peripheral
logic/memory bus PLL, MPC603e processor PLL, and SDRAM clock delay-locked loop (DLL),
respectively. To ensure stability of the internal clocks, the power supplied to the AV
DD
, AV
DD
2, and LAV
DD
input signals should be filtered of any noise in the 500-KHz to 10-MHz resonant frequency range of the
PLLs. Three separate circuits similar to the one shown in Figure 24 using surface mount capacitors with
minimum effective series inductance (ESL) is recommended for AV
DD
, AV
DD
2, and LAV
DD
power signal
pins. Consistent with the recommendations of Dr. Howard Johnson in
High Speed Digital Design: A
Handbook of Black Magic
(Prentice Hall, 1993), using multiple small capacitors of equal value is
recommended over using multiple values.
The circuits should be placed as close as possible to the respective input signal pins to minimize noise
coupled from nearby circuits. Routing directly as possible from the capacitors to the input signal pins with
minimal inductance of vias is important.
1E
11110
01111
Not usable
Off
Off
1F
11111
11111
Off
Off
Notes:
1. The processor HID1 values only represent the multiplier of the processor’s PLL (memory-to-processor multiplier);
thus, multiple MPC8240 PLL_CFG[0:4] values may have the same processor HID1 value. This implies that system
software cannot read the HID1 register and associate it with a unique PLL_CFG[0:4] value.
2. PLL_CFG[0:4] settings not listed (00110, 01001,
01011, 01101, 01111, 10001, 10011, 10101, 10111, 11001, and
11011) are reserved.
3. In PLL-bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral logic PLL
is disabled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended for hardware
modeling support. The AC timing specifications given in this document do not apply in the PLL-bypass mode.
4. In clock-off mode, no clocking occurs inside the MPC8240 regardless of the PCI_SYNC_IN input.
5. Limited due to maximum memory VCO = 225 MHz.
6. Limited due to minimum CPU VCO = 200 MHz.
7. Limited due to minimum memory VCO = 100 MHz.
8. For clarity, range values are shown rounded down to the nearest whole number (decimal place accuracy removed).
9. Note that the 250-MHz part is available only in the XPC8240RZU
nnnx
number series.
Table 18. MPC8240 Microprocessor PLL Configurations (continued)
Ref.
No.
PLL_CFG
[0:4]
2
CPU
1
HID1
[0:4]
200 MHz Part
8,9
Ratios
3,4
PCI Clock Input
(PCI_SYNC_IN)
Range (MHz)
Peripheral
Logic/ Mem Bus
Clock Range
(MHz)
CPU Clock
Range
(MHz)
PCI-to-Mem
(Mem VCO)
Multiplier
Mem-to-CPU
(CPU VCO)
Multiplier
F
Freescale Semiconductor, Inc.
n
.
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