參數(shù)資料
型號(hào)： MPC8240EC
廠商： Motorola, Inc.
英文描述： Integrated Processor Hardware Specifications
中文描述： 綜合處理器硬件規(guī)格
文件頁(yè)數(shù)： 21/52頁(yè)
文件大?。?/td> 1027K
代理商： MPC8240EC
MOTOROLA
MPC8240 Integrated Processor Hardware Specifications
For More Information On This Product,
Go to: www.freescale.com
21
Electrical and Thermal Characteristics
Table 13 provides the I
2
C output AC timing specifications for the MPC8240.
Table 13. I
2
C Output AC Timing Specifications
14, 15
9216, 10240
21
32
64
16, 17, 3A, 3B, 3C, 3D 12288, 14336, 15360, 16384, 20480, 24576
16
24
48
18, 19
18432, 20480
10
16
32
1A, 1B, 3E, 3F
24576, 28672, 30720, 32768
8
12
24
1C, 1D
36864, 40960
5
8
16
1E, 1F
49152, 61440
4
6
12
Notes:
1. Values are in KHz, unless otherwise specified.
2. FDR Hex and Divider (Dec) values are listed in corresponding order.
3. Multiple Divider (Dec) values will generate the same input frequency, but each Divider (Dec) value will generate a
unique output frequency as shown in Table 13.
At recommended operating conditions (see Table 2) with LV
DD
= 3.3 V ± 0.3 V
Num
Characteristic
Min
Max
Unit
Notes
1
Start condition hold time
(FDR[5] == 0)
×
(D
FDR
/16)/2N + (FDR[5]
== 1)
×
(D
FDR
/16)/2M
—
CLKs
1, 2, 5
2
Clock low period
D
FDR
/2
—
CLKs
1, 2, 5
3
SCL/SDA rise time (from 0.5 to 2.4 V)
—
—
ms
3
4
Data hold time
8.0 + (16
×
2
FDR[4:2]
)
×
(5 –
4({FDR[5],FDR[1]} == b'10) –
3({FDR[5],FDR[1]} == b'11) –
2({FDR[5],FDR[1]} == b'00) –
1({FDR[5],FDR[1]} == b'01))
—
CLKs
1, 2, 5
5
SCL/SDA fall time (from 2.4 to 0.5 V)
—
< 5
ns
4
6
Clock high time
D
FDR
/2
—
CLKs
1, 2, 5
7
Data setup time (MPC8240 as a
master only)
(D
FDR
/2) – (Output data hold time)
—
CLKs
1, 5
8
Start condition setup time (for repeated
start condition only)
D
FDR
+ (Output start condition hold time)
—
CLKs
1, 2, 5
Table 12. MPC8240 Maximum I
2
C Input Frequency (continued)
FDR Hex
2
Divider
3
(Dec)
Maximum I
2
C Input Frequency
1
SDRAM_CLK
@ 33 MHz
SDRAM_CLK
@ 50 MHz
SDRAM_CLK
@ 100 MHz
F
Freescale Semiconductor, Inc.
n
.
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