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參數(shù)資料
| 型號(hào)： | MPC8569CVTANKGA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | RISC PROCESSOR, PBGA783 |
| 封裝： | 29 X 29 MM, 1 MM PITCH, PLASTIC, BGA-783 |
| 文件頁(yè)數(shù)： | 126/126頁(yè) |
| 文件大?。?/td> | 2847K |
| 代理商： | MPC8569CVTANKGA |
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JTAG Controller
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
99
The following figure provides the AC test load for TDO and the boundary-scan outputs of the device.
Figure 52. AC Test Load for the JTAG Interface
The following figure provides the JTAG clock input timing diagram.
Figure 53. JTAG Clock Input Timing Diagram
The following figure provides the TRST timing diagram.
Figure 54. TRST Timing Diagram
Input hold times
tJTDXKH
10
—
ns
—
Output valid times:
Boundary-scan data
TDO
tJTKLDV
—
15
10
ns
3
Output hold times
tJTKLDX
0—
ns
3
Notes:
1. The symbols used for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing
(JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going to
the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D)
reaching the invalid state (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that in general, the clock
reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
3. All outputs are measured from the midpoint voltage of the falling edge of tTCLK to the midpoint of the signal in question. The
output timings are measured at the pins. All output timings assume a purely resistive 50-
Ω load. Time-of-flight delays must
be added for trace lengths, vias, and connectors in the system.
4. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing
Table 61. JTAG AC Timing Specifications (continued)
For recommended operating conditions, see Table 3
Parameter
Symbol1
Min
Max
Unit
Notes
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
JTAG
tJTKHKL
tJTGR
External Clock
VM
tJTG
tJTGF
VM = Midpoint Voltage (OVDD/2)
TRST
VM = Midpoint Voltage (OVDD/2)
VM
tTRST
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