參數(shù)資料
型號(hào): MPC8569CVTANKGA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: RISC PROCESSOR, PBGA783
封裝: 29 X 29 MM, 1 MM PITCH, PLASTIC, BGA-783
文件頁數(shù): 80/126頁
文件大?。?/td> 2847K
代理商: MPC8569CVTANKGA
Ethernet Interface
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
57
2.6.3.2.1
MII Transmit AC Timing Specifications
The following table provides the MII transmit AC timing specifications.
The following figure shows the MII transmit AC timing diagram.
Figure 15. MII Transmit AC Timing Diagram
2.6.3.2.2
MII Receive AC Timing Specifications
The following table provides the MII receive AC timing specifications.
Table 27. MII Transmit AC Timing Specifications
For recommended operating conditions, see Table 3
Parameter
Symbol
Min
Typ
Max
Unit
Note
TX_CLK clock period 10 Mbps
tMTX
399.96
400
400.04
ns
TX_CLK clock period 100 Mbps
tMTX
39.996
40
40.004
ns
TX_CLK duty cycle
tMTXH/tMTX
35
65
%
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay
tMTKHDX
0
25
ns
TX_CLK data clock rise (20%–80%)
tMTXR
1.0
4.0
ns
TX_CLK data clock fall (80%–20%)
tMTXF
1.0
4.0
ns
Table 28. MII Receive AC Timing Specifications
For recommended operating conditions, see Table 3
Parameter
Symbol
Min
Typ
Max
Unit
Note
RX_CLK clock period 10 Mbps
tMRX
399.96
400
400.04
ns
1
RX_CLK clock period 100 Mbps
tMRX
39.996
40
40.004
ns
1
RX_CLK duty cycle
tMRXH/tMRX
35
65
%
2
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
tMRDVKH
10.0
ns
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
tMRDXKH
10.0
ns
RX_CLK clock rise (20%–80%)
tMRXR
1.0
4.0
ns
2
RX_CLK clock fall time (80%–20%)
tMRXF
1.0
4.0
ns
2
Note:
1. The frequency of RX_CLK should not exceed the frequency of TX_CLK by more than 300 ppm.
2. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.
TX_CLK
TXD[3:0]
tMTKHDX
tMTX
tMTXH
tMTXR
tMTXF
TX_EN
TX_ER
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