參數(shù)資料
型號: MPC8569CVTANKGA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: RISC PROCESSOR, PBGA783
封裝: 29 X 29 MM, 1 MM PITCH, PLASTIC, BGA-783
文件頁數(shù): 91/126頁
文件大小: 2847K
代理商: MPC8569CVTANKGA
Ethernet Interface
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
67
Output differential voltage2, 3, 4
(XVDD-Typ at 1.1 V)
|VOD|
352.0
550.0
797.5
mV
Equalization
setting: 1.0×
323.1
504.9
732.1
Equalization
setting: 1.09×
293.6
458.7
665.1
Equalization
setting: 1.2×
264.7
413.6
599.7
Equalization
setting: 1.33×
234.4
366.3
531.1
Equalization
setting: 1.5×
205.6
321.2
465.7
Equalization
setting: 1.71×
176.0
275.0
398.8
Equalization
setting: 2.0×
Output impedance (single-ended)
RO
40
50
60
Ω
Notes:
1. This does l not align to DC-coupled SGMII.
2. |VOD| = |VSD_TXn – VSD_TXn|. |VOD| is also referred as output differential peak voltage. VTX-DIFFp-p = 2 × |VOD|.
3. The |VOD| value shown in the table assumes the following transmit equalization setting in the XMITEQAB (for SerDes lanes
0 & 1) or XMITEQEF (for SerDes lanes 2 & 3) bit field of the MPC8569E SerDes control register:
The MSB (bit 0) of the above bit field is set to zero (selecting the full VDD-DIFF-p-p amplitude—power up default);
The LSB (bit [1:3]) of the above bit field is set based on the equalization setting shown in table.
4. The |VOD| value shown in the Typ column is based on the condition of XVDD-Typ = 1.0V and 1.1 V, no common mode offset
variation, SerDes transmitter is terminated with 100-
Ω differential load between SD_TX[n] and SD_TX[n].
Table 36. SGMII DC Transmitter Electrical Characteristics (continued)
At recommended operating conditions with XVDD = 1.0 V ± 3% and 1.1 V ± 3%.
Parameter
Symbol
Min
Typ
Max
Unit
Notes
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