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| 型號(hào)： | MPC8569CVTANKGA |
| 廠(chǎng)商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | RISC PROCESSOR, PBGA783 |
| 封裝： | 29 X 29 MM, 1 MM PITCH, PLASTIC, BGA-783 |
| 文件頁(yè)數(shù)： | 74/126頁(yè) |
| 文件大?。?/td> | 2847K |
| 代理商： | MPC8569CVTANKGA |
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DDR2 and DDR3 SDRAM Controller
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
51
NOTE
For the ADDR/CMD setup and hold specifications in Table 20, it is assumed that the clock
control register is set to adjust the memory clocks by applied cycle.
MDQ/MECC/MDM output setup with
respect to MDQS
tDDKHDS,
tDDKLDS
ps
5
800 MHz
667 MHz
533 MHz
400 MHz
2807
3208
4007
4508
538
700
—
MDQ/MECC/MDM output hold with
respect to MDQS
800 MHz
667 MHz
533 MHz
400 MHz
tDDKHDX,
tDDKLDX
2807
3208
4007
4508
538
700
—
ps
5
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs
(A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.
4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD)
from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control
of the MDQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This will typically be set to the same
delay as in DDR_SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in the table assume that these 2
parameters have been set to the same adjustment value. See the MPC8569E PowerQUICC III Integrated Host Processor
Family Reference Manual for a description and understanding of the timing modifications enabled by use of these bits.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe must be centered inside of the data eye at the pins of the microprocessor.
6. Parameters tested in DDR2 mode are to 400, 533, 667, and 800 MHz data rate and in DDR3 mode to 667 and 800 MHz data
rate.
7. DDR3 only
8. DDR2 only
Table 20. DDR2 and DDR3 SDRAM Interface Output AC Timing Specifications6
At recommended operating conditions with GVDD of 1.8 V ± 5% for DDR2 or 1.5 V ± 5% for DDR3.
Parameter
Symbol1
Min
Max
Unit
Notes
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