
1128
SAM9G45 [DATASHEET]
6438K–ATARM–12-Feb-13
46.14 DDRSDRC Timings
The DDRSDRC controller satisfies the timings of standard DDR2, LP-DDR, SDR and LP-SDR modules.
DDR2, LP-DDR and SDR timings are specified by the JEDEC standard.
Supported speed grade limitations:
DDR2-400 limited at 133 MHz clock frequency (1.8V, 30pF on data/control, 10pF on CK/CK#)
LP-DDR (1.8V, 30pF on data/control, 10pF on CK)
Tcyc = 5.0 ns, Fmax = 125 MHz
Tcyc = 6.0 ns, Fmax = 110 MHz
Tcyc = 7.5 ns, Fmax = 95 MHz
SDR-100 (3.3V, 50pF on data/control, 10pF on CK)
SDR-133 (3.3V, 50pF on data/control, 10pF on CK)
LP-SDR-133 (1.8V, 30pF on data/control, 10pF on CK)
46.15 Peripheral Timings
46.15.1
SPI
46.15.1.1
Maximum SPI Frequency
The following formulas give maximum SPI frequency in Master read and write modes and in Slave read and write
modes.
Master Write Mode
The SPI is only sending data to a slave device such as an LCD, for example. The limit is given by SPI
2 (or
SPI
the max SPI frequency is the one from the pad.
Master Read Mode
T
valid is the slave time response to output data after deleting an SPCK edge. For Atmel SPI DataFlash
(AT45DB642D), T
valid (orTv ) is 12 ns Max.
In the formula above, F
SPCKMax = 38.5 MHz @ VDDIO = 3.3V.
Slave Read Mode
In slave mode, SPCK is the input clock for the SPI. The max SPCK frequency is given by setup and hold tim-
ings SPI
7/SPI8(or SPI10/SPI11). Since this gives a frequency well above the pad limit, the limit in slave read
mode is given by SPCK pad.
Slave Write Mode
For 3.3V I/O domain and SPI6, F
SPCKMax = 33 MHz. Tsetup is the setup time from the master before sampling
data.
f
SPCK Max
1
SP I 0 orSPI3
() T
valid
+
----------------------------------------------------------
=
f
SPCK Max
1
SPI 6 orSPI9
() T
setup
+
----------------------------------------------------------
=