1157
SAM9G45 [DATASHEET]
6438K–ATARM–12-Feb-13
49.2.9
USB High Speed Host Port (UHPHS) and Device Port (UDPHS)
49.2.9.1
UHPHS/UDPHS: USB Does Not Start after Power-up
The USB may not start properly at first use after power-up.
Booting out of the internal ROM fixes this issue because the workaround below is applied in the ROM Code.
Problem Fix/Workaround
There are two possible workarounds:
1.
Apply a hardware reset (NRST) after power-up
or:
2.
Activate the PLLUTMI twice, following the procedure below:
a.
Start The UTMI PLL an wait for the PLL lock bit
b.
Disable the UTMI PLL and wait 10 μ seconds minimum
c.
Restart the UTMI PLL and wait for the PLL Lock bit
Below is a possible implementation of the workaround:
/* First enable the UTMI PLL */
AT91C_BASE_PMC->CKGR_UCKR |= (AT91C_CKGR_UCKR_PLLCOUNT & (0x3 << 20)) |
AT91C_CKGR_UCKR_UPLLEN;
tmp =0;
while (((AT91C_BASE_PMC->PMC_SR & AT91C_PMC_SR_LOCKU) == 0) && (tmp++ < DELAY));
/* Disable the PLLUTMI and wait 10s min*/
AT91C_BASE_PMC->CKGR_UCKR &= ~AT91C_CKGR_UCKR_UPLLEN;
tmp = 0;
while(tmp++ < DELAY2); // DELAY2 must be defined to fit the 10 s min;
/* Re- enable the UTMI PLL and wait for the PLL lock status*/
AT91C_BASE_PMC->CKGR_UCKR |= (AT91C_CKGR_UCKR_PLLCOUNT & (0x3 << 20)) |
AT91C_CKGR_UCKR_UPLLEN;
tmp =0;
while (((AT91C_BASE_PMC->PMC_SR & AT91C_PMC_SR_LOCKU) == 0) && (tmp++ < DELAY));
49.2.9.2
UHPHS/UDPHS: Bad Lock of the USB High speed transceiver DLL
The DLL used to oversample the incoming bitstream may not lock in the correct phase, leading to a bad reception
of the incoming packets.
This issue may occur after the USB device resumes from the Suspend mode.
The DLL is used only in the High Speed mode, meaning the Full Speed mode is not impacted by this issue.
This issue may occur on the USB device after a reset leading to a SAM-BA connection issue.
Problem Fix/Workaround:
To prevent a SAM-BA execution issue, the USB device must be connected via a USB Full Speed hub to the PC.
At application level, the DLL can be re-initialized in the correct state by toggling the BIASEN bit (high -> low ->
high) when resuming from the Suspend mode.
The BIASEN bit is located in the CKGR_UCKR register in the PMC user interface.
The function below can be used to generate the pulse on the bias signal.
void generate_pulse_bias(void)