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型號(hào)：	MQ80C32-20
廠商：	ATMEL CORP
元件分類(lèi)：	微控制器/微處理器
英文描述：	8-BIT, 20 MHz, MICROCONTROLLER, CQFP44
封裝：	CERAMIC, QFP-44
文件頁(yè)數(shù)：	446/1185頁(yè)
文件大?。?/td>	5451K
代理商：	MQ80C32-20

SAM9G45 [DATASHEET]

6438K–ATARM–12-Feb-13

from the OSCOUNT value. Since the OSCOUNT value is coded with 8 bits, the maximum startup time is about 62

When the counter reaches 0, the MOSCS bit is set, indicating that the main clock is valid. Setting the MOSCS bit in

PMC_IMR can trigger an interrupt to the processor.

Main Oscillator Bypass

The user can input a clock on the device instead of connecting a crystal. In this case, the user has to provide the

external clock signal on the XIN pin. The input characteristics of the XIN pin under these conditions are given in the

product electrical characteristics section. The programmer has to be sure to set the OSCBYPASS bit to 1 and the

MOSCEN bit to 0 in the Main OSC register (CKGR_MOR) for the external clock to operate properly.

Divider and PLLA Block

The PLLA embeds an input divider to increase the accuracy of the resulting clock signals. However, the user must

respect the PLLA minimum input frequency when programming the divider.

The PLLA embeds also an output divisor by 2.

Figure 25-6 shows the block diagram of the divider and PLLA block.

Figure 25-6. Divider and PLLA Block Diagram

Divider and Phase Lock Loop Programming

The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the output of the cor-

responding divider and the PLL output is a continuous signal at level 0. On reset, each DIV field is set to 0, thus the

corresponding PLL input clock is set to 0.

The PLLA allows multiplication of the divider’s outputs. The PLLA clock signal has a frequency that depends on the

respective source signal frequency and on the parameters DIVA and MULA. The factor applied to the source signal

frequency is (MULA + 1)/DIVA. When MULA is written to 0, the PLLA is disabled and its power consumption is

saved. Re-enabling the PLLA can be performed by writing a value higher than 0 in the MUL field.

Whenever the PLLA is re-enabled or one of its parameters is changed, the LOCKA bit in PMC_SR is automatically

cleared. The values written in the PLLACOUNT field in CKGR_PLLAR are loaded in the PLLA counter. The PLLA

counter then decrements at the speed of the Slow Clock until it reaches 0. At this time, the LOCK bit is set in

PMC_SR and can trigger an interrupt to the processor. The user has to load the number of Slow Clock cycles

required to cover the PLLA transient time into the PLLACOUNT field.

The PLLA clock can be divided by 2 by writing the PLLADIV2 bit in PMC_MCKR register.

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