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參數(shù)資料
| 型號： | MSC8103VT1100F |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 11/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 16BIT 275MHZ 332-FCPBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | StarCore |
| 類型： | SC140 內(nèi)核 |
| 接口： | 通信處理器模塊（CPM） |
| 時鐘速率： | 275MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 512kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.60V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 332-BFBGA，F(xiàn)CPBGA |
| 供應(yīng)商設(shè)備封裝： | 332-FCBGA（17x17） |
| 包裝： | 托盤 |
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MSC8103 Network Digital Signal Processor, Rev. 12
1-10
Freescale Semiconductor
Signals/Connections
D56
HACK/HACK
HRRQ/HRRQ
Input/Output
Output
Data Bus Bit 56
In write transactions the bus master drives the valid data on this pin. In read transactions the slave
drives the valid data on this pin.
Host Acknowledge3
When the HDI16 is programmed to interface with a single host request host bus, this pin is the host
acknowledge Schmitt trigger input (HACK). The polarity of the host acknowledge is programmable.
Receive Host Request3
When the HDI16 is programmed to interface with a double host request host bus, this pin is the
receive host request output (HRRQ/HRRQ). The signal can be programmed as driven or open drain.
The polarity of the host request is programmable.
D57
HDSP
Input/Output
Input
Data Bus Bit 57
In write transactions the bus master drives the valid data on this pin. In read transactions the slave
drives the valid data on this pin.
Host Data Strobe Polarity3
When the HDI16 interface is enabled, this pin is the host data strobe polarity (HDSP).
D58
HDDS
Input/Output
Input
Data Bus Bit 58
In write transactions the bus master drives the valid data on this pin. In read transactions the slave
drives the valid data on this pin.
Host Dual Data Strobe3
When the HDI16 interface is enabled, this pin is the host dual data strobe (HDDS).
D59
H8BIT
Input/Output
Input
Data Bus Bit 59
In write transactions the bus master drives the valid data on this pin. In read transactions the slave
drives the valid data on this pin.
H8BIT3
When the HDI16 interface is enabled, this bit determines if the interface is in 8-bit or 16-bit mode.
D60
HCS2
Input/Output
Input
Data Bus Bit 60
In write transactions the bus master drives the valid data on this pin. In read transactions the slave
drives the valid data on this pin.
Host Chip Select 3
When the HDI16 interface is enabled, this is one of the two chip-select pins. The HDI16 chip select
is a logical OR of HCS1 and HCS2.
D[61–63]
Reserved
Input/Output
Data Bus Bits 61–63
Used only in 60x-mode-only mode. In write transactions the bus master drives the valid data on this
bus. In read transactions the slave drives the valid data on this bus.
These dedicated signals are reserved when the HDI16 is enabled.3
Reserved
DP0
EXT_BR2
Input
Input/Output
Input
The primary configuration is reserved.
Data Parity 01
The agent that drives the data bus also drives the data parity signals. The value driven on the data
parity zero pin should give odd parity (odd number of ones) on the group of signals that includes
data parity 0 and D[0–7].
External Bus Request 21,2
An external master asserts this pin to request bus ownership from the internal arbiter.
Table 1-5.
System Bus, HDI16, and Interrupt Signals (Continued)
Signal
Data Flow
Description
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