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| 型號： | MSC8103VT1100F |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 14/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 16BIT 275MHZ 332-FCPBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | StarCore |
| 類型： | SC140 內(nèi)核 |
| 接口： | 通信處理器模塊（CPM） |
| 時(shí)鐘速率： | 275MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 512kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.60V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 332-BFBGA，F(xiàn)CPBGA |
| 供應(yīng)商設(shè)備封裝： | 332-FCBGA（17x17） |
| 包裝： | 托盤 |
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Memory Controller Signals
MSC8103 Network Digital Signal Processor, Rev. 12
Freescale Semiconductor
1-13
1.5 Memory Controller Signals
Refer to the memory controller chapter in the MSC8103 Reference Manual (MSC8103RM/D) for detailed
information about configuring these signals.
IRQ7
INT_OUT
Input
Output
Interrupt Request 71
One of eight external lines that can request a service routine, via the internal interrupt controller,
from the SC140 core.
Interrupt Output1
Driven from the MSC8103 internal interrupt controller. Assertion of this output indicates that an
unmasked interrupt is pending in the MSC8103 internal interrupt controller.
Notes:
1.
See the SIU chapter in the MSC8103 Reference Manual for details on how to configure these pins.
2.
When used as the bus control arbiter for the system bus, the MSC8103 can support up to three external bus masters. Each
master uses its own set of Bus Request, Bus Grant, and Data Bus Grant signals (BR/BG/DBG,
EXT_BR2/EXT_BG2/EXT_DBG2, and EXT_BR3/EXT_BG3/EXT_DBG3). Each of these signal sets must be configured to
indicate whether the external master is or is not a MSC8103 master device. See the Bus Configuration Register (BCR)
description in the SIU chapter in the MSC8103 Reference Manual for details on how to configure these pins. The second and
third set of pins is defined by EXT_xxx to indicate that they can only be used with external master devices. The first set of pins
(BR/BG/DBG) have a dual function. When the MSC8103 is not the bus arbiter, these signals (BR/BG/DBG) are used by the
MSC8103 to obtain master control of the bus.
3.
See the host interface (HDI16) chapter in the MSC8103 Reference Manual for details on how to configure these pins.
Table 1-6.
Memory Controller Signals
Signal
Data Flow
Description
CS[0–7]
Output
Chip Select
Enable specific memory devices or peripherals connected to MSC8103 buses.
BCTL1
Output
Buffer Control 1
Controls buffers on the data bus. Usually used with BCTL0. The exact function of this pin is defined
by the value of SIUMCR[BCTLC]. See the System Interface Unit (SIU) chapter in the MSC8103
Reference Manual for details.
BADDR[27–28]
Output
Burst Address 27–28
Two of five outputs of the memory controller. These pins connect directly to memory devices
controlled by the MSC8103 memory controller.
ALE
Output
Address Latch Enable
Controls the external address latch used in external master bus configuration.
BCTL0
Output
Buffer Control 0
Controls buffers on the data bus. The exact function of this pin is defined by the value of
SIUMCR[BCTLC]. See the System Interface Unit (SIU) chapter in the MSC8103 Reference Manual
for details.
PWE[0–7]
PSDDQM[0–7]
PBS[0–7]
Output
Bus Write Enable
Outputs of the bus General-Purpose Chip-select Machine (GPCM). These pins select byte lanes for
write operations.
Bus SDRAM DQM
Outputs of the SDRAM control machine. These pins select specific byte lanes of SDRAM devices.
Bus UPM Byte Select
Outputs of the User-Programmable Machine (UPM) in the memory controller. These pins select
specific byte lanes during memory operations. The timing of these pins is programmed in the UPM.
The actual driven value depends on the address and size of the transaction and the port size of the
accessed device.
Table 1-5.
System Bus, HDI16, and Interrupt Signals (Continued)
Signal
Data Flow
Description
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