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| 型號： | MSC8103VT1100F |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 3/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 16BIT 275MHZ 332-FCPBGA |
| 標準包裝： | 90 |
| 系列： | StarCore |
| 類型： | SC140 內核 |
| 接口： | 通信處理器模塊（CPM） |
| 時鐘速率： | 275MHz |
| 非易失內存： | 外部 |
| 芯片上RAM： | 512kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.60V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 332-BFBGA，F(xiàn)CPBGA |
| 供應商設備封裝： | 332-FCBGA（17x17） |
| 包裝： | 托盤 |
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MSC8103 Network Digital Signal Processor, Rev. 12
4-2
Freescale Semiconductor
Design Considerations
Select the bootstrap diodes such that a nominal VDD/VCCSYN is sourced from the VDDH power supply until the
VDD/VCCSYN power supply becomes active. In Figure 4-1, four MUR420 Schottky barrier diodes are connected in
series; each has a forward voltage (VF) of 0.6 V at high currents, so these diodes provide a 2.4 V drop, maintaining
0.9 V on the 1.6 V power line. Once the core/PLL power supply stabilizes at 1.6 V, the bootstrap diodes will be
reverse biased with negligible leakage current. The VF should be effective at the current levels required by the
processor. Do not use diodes with a nominal VF that drops too low at high current.
4.3 Power Considerations
The internal power dissipation consists of three components:
PINT = PCORE + PSIU + PCPM
Power dissipation depends on the operating frequency of the different portions of the chip. Table 2-5 provides
typical power values at the specified operating frequencies. To determine the typical power dissipation for a given
set of frequencies, use the following equations:
PCORE (f) = ((PCORE – PLCO)/fCORE) × fCOREA + PLCO
PCPM (f) = ((PCPM – PLCP)/fCPM) × fCPMA + PLCP
PSIU (f) = ((PSIU – PLSI)/fSIU) × fSIUA + PLSI
Where:
fCORE is the core frequency, fSIU is the SIU frequency, and fCPM is the CPM frequency specified in Table 2-5 in
MHz
fCOREA is the actual core frequency, FSIUA is the actual SIU frequency, and FCPMA is the actual CPM frequency
in MHz
All power numbers are in mW
Power consumption is assumed to be linear with frequency. The first part of each equation computes a mw/MHz
value that is then scaled based on the actual frequency used.
To determine a total power dissipation in a specific application, you must add the power values derived from the
above set of equations to the value derived for I/O power consumption using the following equation for each output
pin:
P = C
× VDDH2 × f × 10–3
Equation 2
Where: P = power in mW, C = load capacitance in pF, f = output switching frequency in MHz.
For an application in which external data memory is used in a 32-bit single bus mode and no other outputs are
active, the core runs at 200 MHz, the CPM runs at 100 MHz and the SIU runs at 50 MHz, power dissipation is
calculated as follows:
Assumptions:
External data memory is accessed every second cycle with 10% of address pins switching.
External data memory writes occurs once every eight cycles with 50% of data pins switching.
Each address and data pin has a 30 pF total load at the pin.
The application operates at VDDH = 3.3 V.
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