參數(shù)資料
型號: MSC8103VT1100F
廠商: Freescale Semiconductor
文件頁數(shù): 2/104頁
文件大?。?/td> 0K
描述: IC DSP 16BIT 275MHZ 332-FCPBGA
標準包裝: 90
系列: StarCore
類型: SC140 內核
接口: 通信處理器模塊(CPM)
時鐘速率: 275MHz
非易失內存: 外部
芯片上RAM: 512kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.60V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 332-BFBGA,F(xiàn)CPBGA
供應商設備封裝: 332-FCBGA(17x17)
包裝: 托盤
MSC8103 Network Digital Signal Processor, Rev. 12
1-6
Freescale Semiconductor
Signals/Connections
1.4 System Bus, HDI16, and Interrupt Signals
The system bus, HDI16, and interrupt signals are grouped together because they use a common set of signal lines.
Individual assignment of a signal to a specific signal line is configured through registers in the System Interface
Unit (SIU) and the Host Interface (HDI16). 1-5 describes the signals in this group.
Note:
To boot from the host interface, the HDI16 must be enabled by pulling up the HPE signal line during
PORESET
. The configuration word must then be loaded from the host. The configuration word must set the
Internal Space Port Size bit in the Bus Control Register (BCR[ISPS]) to change the system data bus width
from 64 bits to 32 bits and reassign the upper 32 bits to their HDI16 functions. Never set the Host Port
Enable (HEN) bit in the Host Port Control Register (HPCR) to enable the HDI16, unless the bus size is
first changed from 64 bits to 32 bits. Otherwise, unpredictable operation may occur.
BTM[0–1]
EE41
EE51
Input
Output
Input
Output
Boot Mode 0–1
Determines the MSC8103 boot mode when PORESET is deasserted. See the emulation and debug
chapter in the SC140 DSP Core Reference Manual for details on how to set these pins.
EOnCE Event 4
After PORESET is deasserted, you can configure EE4 as an input (default) or an output. See the
emulation and debug chapter in the SC140 DSP Core Reference Manual for details on the ETRSMT
Register.
Enable Address Event Detection Channel 4 or generate an EOnCE event.
The DSP wrote the EOnCE Transmit Register (ETRSMT). Triggers external debugging equipment.
EOnCE Event 5
After PORESET is deasserted, you can configure EE5 as an input (default) or an output.
Enable Address Event Detection Channel 5.
Detection by Address Event Detection Channel 5. Triggers external debugging equipment.
EED1
Input
Output
Enhanced OnCE (EOnCE) Event Detection
After PORESET is deasserted, you can configure EED as an input (default) or output:
Enable the Data Event Detection Channel.
Detection by the Data Event Detection Channel. Triggers external debugging equipment.
PORESET
Input
Power-On Reset
When asserted, this line causes the MSC8103 to enter power-on reset state.
RSTCONF
Input
Reset Configuration
Used during reset configuration sequence of the chip. A detailed explanation of its function is
provided in the “Power-On Reset Flow” and “Hardware Reset Configuration” sections of the
MSC8103 Reference Manual.
HRESET
Input
Hard Reset
When asserted, this open-drain line causes the MSC8103 to enter the hard reset state.
SRESET
Input
Soft Reset
When asserted, this open-drain line causes the MSC8103 to enter the soft reset state.
Note:
See the emulation and debug chapter in the SC140 DSP Core Reference Manual for details on how to configure these pins.
Table 1-4.
Reset, Configuration, and EOnCE Event Signals (Continued)
Signal Name
Type
Signal Description
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MSC8103VT1200F 功能描述:IC DSP 16BIT 300MHZ 332-FCPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP(數(shù)字式信號處理器) 系列:StarCore 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI,以太網,RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA,F(xiàn)CBGA 供應商設備封裝:431-FCPBGA(20x20) 包裝:托盤
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