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參數(shù)資料
| 型號： | MSC8103VT1100F |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 12/104頁 |
| 文件大小： | 0K |
| 描述： | IC DSP 16BIT 275MHZ 332-FCPBGA |
| 標準包裝： | 90 |
| 系列： | StarCore |
| 類型： | SC140 內(nèi)核 |
| 接口： | 通信處理器模塊（CPM） |
| 時鐘速率： | 275MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 512kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.60V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 332-BFBGA，F(xiàn)CPBGA |
| 供應商設備封裝： | 332-FCBGA（17x17） |
| 包裝： | 托盤 |
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System Bus, HDI16, and Interrupt Signals
MSC8103 Network Digital Signal Processor, Rev. 12
Freescale Semiconductor
1-11
IRQ1
DP1
EXT_BG2
Input
Input/Output
Output
Interrupt Request 11
One of eight external lines that can request a service routine, via the internal interrupt controller,
from the SC140 core.
Data Parity 11
The agent that drives the data bus also drives the data parity signals. The value driven on the data
parity one pin should give odd parity (odd number of ones) on the group of signals that includes data
parity 1 and D[8–15].
External Bus Grant 21,2
The MSC8103 asserts this pin to grant bus ownership to an external bus master.
IRQ2
DP2
EXT_DBG2
Input
Input/Output
Output
Interrupt Request 21
One of eight external lines that can request a service routine, via the internal interrupt controller,
from the SC140 core.
Data Parity 21
The agent that drives the data bus also drives the data parity signals. The value driven on the data
parity two pin should give odd parity (odd number of ones) on the group of signals that includes data
parity 2 and D[16–23].
External Data Bus Grant 21,2
The MSC8103 asserts this pin to grant data bus ownership to an external bus master.
IRQ3
DP3
EXT_BR3
Input
Input/Output
Input
Interrupt Request 31
One of eight external lines that can request a service routine, via the internal interrupt controller,
from the SC140 core.
Data Parity 31
The agent that drives the data bus also drives the data parity signals. The value driven on the data
parity three pin should give odd parity (odd number of ones) on the group of signals that includes
data parity 3 and D[24–31].
External Bus Request 31,2
An external master asserts this pin to request bus ownership from the internal arbiter.
IRQ4
DP4
DREQ3
EXT_BG3
Input
Input/Output
Input
Output
Interrupt Request 41
One of eight external lines that can request a service routine, via the internal interrupt controller,
from the SC140 core.
Data Parity 41
The agent that drives the data bus also drives the data parity signals. The value driven on the data
parity four pin should give odd parity (odd number of ones) on the group of signals that includes data
parity 4 and D[32–39].
DMA Request 31
An external peripheral uses this pin to request DMA service.
External Bus Grant 31,2
The MSC8103 asserts this pin to grant bus ownership to an external bus master.
Table 1-5.
System Bus, HDI16, and Interrupt Signals (Continued)
Signal
Data Flow
Description
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