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參數(shù)資料
| 型號(hào)： | MSC8256TVT800B |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 0-BIT, OTHER DSP, PBGA783 |
| 封裝： | 29 X 29 MM, LEAD FREE, PLASTIC, FCBGA-783 |
| 文件頁數(shù)： | 32/68頁 |
| 文件大?。?/td> | 910K |
| 代理商： | MSC8256TVT800B |
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MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 3
Electrical Characteristics
Freescale Semiconductor
38
Note:
For the ADDR/CMD setup and hold specifications in Table 21, it is assumed that the clock control register is set to
adjust the memory clocks by applied cycle.
Notes:
1.
The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs
(A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference (K)
goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2.
All MCK/MCK referenced measurements are made from the crossing of the two signals.
3.
ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.
4.
Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD)
from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control of
the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in the
CLK_CNTL register. The timing parameters listed in the table assume that these two parameters have been set to the same
adjustment value. See the MSC8256 Reference Manual for a description and understanding of the timing modifications
enabled by use of these bits.
5.
Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the MSC8256.
6.
At recommended operating conditions with VDDDDR (1.5 V or 1,8 V) ± 5%.
Figure 12. MCK to MDQS Timing
Table 21. DDR SDRAM Output AC Timing Specifications (continued)
Parameter
Symbol 1
Min
Max
Unit
Notes
MDQS
MCK[n]
tMCK
tDDKHMHmax) = 0.6 ns or 0.375 ns
tDDKHMH(min) = –0.6 ns or –0.375 ns
MDQS
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