參數(shù)資料
型號(hào)： MSC8256TVT800B
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 0-BIT, OTHER DSP, PBGA783
封裝： 29 X 29 MM, LEAD FREE, PLASTIC, FCBGA-783
文件頁(yè)數(shù)： 44/68頁(yè)
文件大小： 910K
代理商： MSC8256TVT800B
Electrical Characteristics
MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 3
Freescale Semiconductor
49
2.6.6
SPI Timing
Table 36 lists the SPI input and output AC timing specifications.
Figure 26 provides the AC test load for the SPI.
Figure 26. SPI AC Test Load
Figure 27 and Figure 28 represent the AC timings from Table 36. Note that although the specifications generally reference the
rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge.
Figure 27 shows the SPI timings in slave mode (external clock).
Figure 27. SPI AC Timing in Slave Mode (External Clock)
Figure 28 shows the SPI timings in master mode (internal clock).
Table 36. SPI AC Timing Specifications
Parameter
Symbol 1
Min
Max
Unit
Note
SPI outputs valid—Master mode (internal clock) delay
tNIKHOV
—6
ns
2
SPI outputs hold—Master mode (internal clock) delay
tNIKHOX
0.5
—
ns
2
SPI outputs valid—Slave mode (external clock) delay
tNEKHOV
—12
ns
2
SPI outputs hold—Slave mode (external clock) delay
tNEKHOX
2—
ns
2
SPI inputs—Master mode (internal clock) input setup time
tNIIVKH
12
—
ns
—
SPI inputs—Master mode (internal clock) input hold time
tNIIXKH
0—
ns
—
SPI inputs—Slave mode (external clock) input setup time
tNEIVKH
4—
ns
—
SPI inputs—Slave mode (external clock) input hold time
tNEIXKH
2—
ns
—
Notes:
1.
The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,
tNIKHOX symbolizes the internal timing (NI) for the time SPICLK clock reference (K) goes to the high state (H) until
outputs (O) are invalid (X).
2.
Output specifications are measured from the 50% level of the rising edge of SPICLK to the 50% level of the signal.
Timings are measured at the pin.
Output
Z0 = 50 Ω
VDDIO/2
RL = 50 Ω
SPICLK (input)
tNEIXKH
tNEKHOV
Input Signals:
SPIMOSI
(See note)
Output Signals:
SPIMISO
(See note)
tNEIVKH
tNEKHOX
Note: measured with SPMODE[CI] = 0, SPMODE[CP] = 0
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