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參數(shù)資料
| 型號(hào)： | MSC8256TVT800B |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 0-BIT, OTHER DSP, PBGA783 |
| 封裝： | 29 X 29 MM, LEAD FREE, PLASTIC, FCBGA-783 |
| 文件頁(yè)數(shù)： | 54/68頁(yè) |
| 文件大?。?/td> | 910K |
| 代理商： | MSC8256TVT800B |
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MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 3
Hardware Design Considerations
Freescale Semiconductor
58
3.5
Connectivity Guidelines
Note:
Although the package actually uses a ball grid array, the more conventional term pin is used to denote signal
connections in this discussion.
First, select the pin multiplexing mode to allocate the required I/O signals. Then use the guidelines presented in the following
subsections for board design and connections. The following conventions are used in describing the connectivity requirements:
1.
GND indicates using a 10 k
Ω pull-down resistor (recommended) or a direct connection to the ground plane. Direct
connections to the ground plane may yield DC current up to 50 mA through the I/O supply that adds to overall power
consumption.
2.
VDD indicates using a 10 kΩ pull-up resistor (recommended) or a direct connection to the appropriate power supply.
Direct connections to the supply may yield DC current up to 50 mA through the I/O supply that adds to overall power
consumption.
3.
Mandatory use of a pull-up or pull-down resistor is clearly indicated as “pull-up/pull-down.” For buses, each pin on
the bus should have its own resistor.
4.
NC indicates “not connected” and means do not connect anything to the pin.
5.
The phrase “in use” indicates a typical pin connection for the required function.
Note:
Please see recommendations #1 and #2 as mandatory pull-down or pull-up connection for unused pins in case of
subset interface connection.
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