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參數(shù)資料
| 型號： | MSC8256TVT800B |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 0-BIT, OTHER DSP, PBGA783 |
| 封裝： | 29 X 29 MM, LEAD FREE, PLASTIC, FCBGA-783 |
| 文件頁數(shù)： | 35/68頁 |
| 文件大小： | 910K |
| 代理商： | MSC8256TVT800B |
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MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 3
Electrical Characteristics
Freescale Semiconductor
40
Table 22 provides the DDR2 differential specifications for the differential signals MDQS/MDQS and MCK/MCK.
Table 23 provides the DDR3 differential specifications for the differential signals MDQS/MDQS and MCK/MCK.
2.6.2
HSSI AC Timing Specifications
The following subsections define the AC timing requirements for the SerDes reference clocks, the PCI Express data lines, the
Serial RapidIO data lines, and the SGMII data lines.
2.6.2.1
AC Requirements for SerDes Reference Clock
Table 24 lists AC requirements for the SerDes reference clocks.
Note:
Specifications are valid at the recommended operating conditions listed in Table 3.
Table 22. DDR2 SDRAM Differential Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
Input AC differential cross-point voltage
VIXAC
0.5
× GVDD – 0.175
0.5
× GVDD + 0.175
V
Output AC differential cross-point voltage
VOXAC
0.5
× GVDD – 0.125
0.5
× GVDD + 0.125
V
Table 23. DDR3 SDRAM Differential Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
Input AC differential cross-point voltage
VIXAC
0.5
× GVDD – 0.150
0.5
× GVDD + 0.150
V
Output AC differential cross-point voltage
VOXAC
0.5
× GVDD – 0.115
0.5
× GVDD + 0.115
V
Table 24. SR[1–2]_REF_CLK and SR[1–2]_REF_CLK Input Clock Requirements
Parameter
Symbol
Min
Typical
Max
Units
Notes
SR[1–2]_REF_CLK/SR[1–2]_REF_CLK
frequency range
tCLK_REF
—
100/125
—
MHz
1
SR[1–2]_REF_CLK/SR[1–2]_REF_CLK clock
frequency tolerance
tCLK_TOL
–350
—
350
ppm
—
SR[1–2]_REF_CLK/SR[1–2]_REF_CLK
reference clock duty cycle (measured at 1.6 V)
tCLK_DUTY
40
50
60
%
—
SR[1–2]_REF_CLK/SR[1–2]_REF_CLK max
deterministic peak-peak jitter at 10-6 BER
tCLK_DJ
——
42
ps
—
SR[1–2]_REF_CLK/SR[1–2]_REF_CLK total
reference clock jitter at 10-6 BER (peak-to-peak
jitter at ref_clk input)
tCLK_TJ
——
86
ps
2
SR[1–2]_REF_CLK/SR[1–2]_REF_CLK
rising/falling edge rate
tCLKRR/tCLKFR
1—4
V/ns
3
Differential input high voltage
VIH
200
—
mV
4
Differential input low voltage
VIL
—
–200
mV
4
Rising edge rate (SR[1–2]_REF_CLK) to falling
edge rate (SR[1–2]_REF_CLK) matching
Rise-Fall
Matching
——
20
%
5, 6
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