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參數(shù)資料
| 型號(hào)： | MSC8256TVT800B |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 0-BIT, OTHER DSP, PBGA783 |
| 封裝： | 29 X 29 MM, LEAD FREE, PLASTIC, FCBGA-783 |
| 文件頁數(shù)： | 36/68頁 |
| 文件大?。?/td> | 910K |
| 代理商： | MSC8256TVT800B |
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Electrical Characteristics
MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 3
Freescale Semiconductor
41
Notes:
1.
Caution: Only 100 and 125 have been tested. Other values will not work correctly with the rest of the system.
2.
Limits from PCI Express CEM Rev 1.0a
3.
Measured from –200 mV to +200 mV on the differential waveform (derived from SR[1–2]_REF_CLK minus
SR[1–2]_REF_CLK). The signal must be monotonic through the measurement region for rise and fall time. The 400 mV
measurement window is centered on the differential zero crossing. See Figure 16.
4.
Measurement taken from differential waveform
5.
Measurement taken from single-ended waveform
6.
Matching applies to rising edge for SR[1–2]_REF_CLK and falling edge rate for SR[1–2]_REF_CLK. It is measured using a
200 mV window centered on the median cross point where SR[1–2]_REF_CLK rising meets SR[1–2]_REF_CLK falling. The
median cross point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations. The
rise edge rate of SR[1–2]_REF_CLK should be compared to the fall edge rate of SR[1–2]_REF_CLK; the maximum allowed
difference should not exceed 20% of the slowest edge rate. See Figure 17.
Figure 16. Differential Measurement Points for Rise and Fall Time
Figure 17. Single-Ended Measurement Points for Rise and Fall Time Matching
Table 24. SR[1–2]_REF_CLK and SR[1–2]_REF_CLK Input Clock Requirements (continued)
Parameter
Symbol
Min
Typical
Max
Units
Notes
VIH = +200 mV
VIL = –200 mV
0.0 V
SR[1–2]_REF_CLK
–
SR[1–2]_REF_CLK
Fall Edge Rate
Rise Edge Rate
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