參數(shù)資料
型號(hào)： MT18VDVF6472DG-265XX
元件分類(lèi)： DRAM
英文描述： 64M X 72 DDR DRAM MODULE, 0.75 ns, DMA184
封裝： DIMM-184
文件頁(yè)數(shù)： 15/38頁(yè)
文件大小： 713K
代理商： MT18VDVF6472DG-265XX
PDF: 09005aef81c73825/Source: 09005aef81c73837
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DVF18C64_128x72D_2.fm - Rev. A 8/05 EN
22
2003, 2004, 2005 Micron Technology, Inc. All rights reserved.
512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
Notes
1. All voltages referenced to VSS.
2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted
at nominal reference/supply voltage levels, but the related specifications and device
operation are guaranteed for the full voltage range specified.
3. Outputs measured with equivalent load:
4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment,
but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and
parameter specifications are guaranteed for the specified AC input levels under normal
use conditions. The minimum slew rate for the input signals used to test the device is
1V/ns in the range between VIL(AC) and VIH(AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e.,
the receiver will effectively switch as a result of the signal crossing the AC input level,
and will remain in that state as long as the signal does not ring back above [below] the
DC input LOW [HIGH] level).
6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in
the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not
exceed ±2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed ±25mV for DC
error and an additional ±25mV for AC noise. This measurement is to be taken at the
nearest VREF by-pass capacitor.
7. VTT is not applied directly to the device. VTT is a system supply for signal termination
resistors, is expected to be set equal to VREF and must track variations in the DC level
of VREF.
8. IDD is dependent on output loading and cycle rates. Specified values are obtained
with minimum cycle time at CL = 2 for -262, and -26A, CL = 2.5 for-335 and -265 with
the outputs open.
9. Enables on-chip refresh and address counters.
10. IDD specifications are tested after the device is properly initialized, and is averaged at
the defined cycle rate.
11. This parameter is sampled. VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V, VREF = VSS, f = 100
MHz, TA = 25°C, VOUT(DC) = VDDQ/2, VOUT (peak to peak) = 0.2V. DM input is grouped
with I/O pins, reflecting the fact that they are matched in loading.
12. For slew rates less than 1 V/ns and greater than or equal to 0.5 V/ns. If slew rate is less
than 0.5 V/ns, timing must be derated: tIS has an additional 50ps per each 100 mV/ns
reduction in slew rate from 500 mV/ns, while tIH is unaffected. If slew rate exceeds 4.5
V/ns, functionality is uncertain. For -335, slew rates must be ≥ 0.5 V/ns.
13. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at
which CK and CK# cross; the input reference level for signals other than CK/CK# is
VREF.
14. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period
before VREF stabilizes, CKE ≤ 0.3 x VDDQ is recognized as LOW.
15. The output timing reference level, measured at the timing reference point indicated in
Note 3, is VTT.
Output
(VOUT)
Reference
Point
50Ω
VTT
30pF
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