參數(shù)資料
型號(hào): MT18VDVF6472DG-265XX
元件分類: DRAM
英文描述: 64M X 72 DDR DRAM MODULE, 0.75 ns, DMA184
封裝: DIMM-184
文件頁(yè)數(shù): 5/38頁(yè)
文件大小: 713K
代理商: MT18VDVF6472DG-265XX
PDF: 09005aef81c73825/Source: 09005aef81c73837
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DVF18C64_128x72D_2.fm - Rev. A 8/05 EN
13
2003, 2004, 2005 Micron Technology, Inc. All rights reserved.
512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
Mode Register Definition
Notes: 1. For a burst length of two, A1–Ai select the two-data-element block; A0 selects the first
access within the block.
2. For a burst length of four, A2–Ai select the four-data-element block; A0–A1 select the first
access within the block.
3. For a burst length of eight, A3–Ai select the eight-data-element block; A0–A2 select the
first access within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the follow-
ing access wraps within the block.
5. i = 9 for 512MB
i = 9, 11 for 1GB
Table 5:
Burst Definition Table
Burst Length
Starting Column
Address
Order of Accesses Within a Burst
Type = Sequential
Type = Interleaved
2
A0
00-1
0-1
11-0
1-0
4
A1
A0
0
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
1
3-0-1-2
3-2-1-0
8
A2
A1
A0
0
0-1-2-3-4-5-6-7
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Table 6:
CAS Latency Table
Speed
Allowable Operating Clock Frequency (MHz)
CL = 2
CL = 2.5
-335
75
≤ f ≤ 133
75
≤ f ≤ 166
-262
75
≤ f ≤ 133
75
≤ f ≤ 133
-26A
75
≤ f ≤ 133
75
≤ f ≤ 133
-265
75
≤ f ≤ 100
75
≤ f ≤ 133
-202
75
≤ f ≤ 100
75
≤ f ≤ 125
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