- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄296641 > MT18VDVF6472DG-265XX 64M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 PDF資料下載
參數(shù)資料
| 型號： | MT18VDVF6472DG-265XX |
| 元件分類： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| 封裝： | DIMM-184 |
| 文件頁數(shù)： | 29/38頁 |
| 文件大?。?/td> | 713K |
| 代理商： | MT18VDVF6472DG-265XX |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁當(dāng)前第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁
PDF: 09005aef81c73825/Source: 09005aef81c73837
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DVF18C64_128x72D_2.fm - Rev. A 8/05 EN
35
2003, 2004, 2005 Micron Technology, Inc. All rights reserved.
512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
Serial Presence-Detect
Notes: 1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1
and the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a
write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis-
tor, and the EEPROM does not respond to its slave address.
Table 19:
Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
Parameter/Condition
Symbol
Min
Max
Units
Supply Voltage
VDDSPD
2.3
3.6
V
Input High Voltage: Logic 1; All inputs
VIH
VDDSPD X 0.7
VDDSPD + 0.5
V
Input Low Voltage: Logic 0; All inputs
VIL
-0.6
VDDSPD x 0.3
V
Output Low Voltage: IOUT = 3mA
VOL
–0.4
V
Input Leakage Current: VIN = GND to VDD
ILI
0.10
3
A
Output Leakage Current: VOUT = GND to VDD
ILO
0.05
3
A
Standby Current: SCL = SDA = VDD - 0.3V; All other inputs = VDD or VSS
ISB
1.6
4
A
Power Supply Current, READ: SCL clock frequency = 100 KHz
ICC
R
0.4
1
mA
Powr Supply Current, WRITE: SCL clock frequency = 100 KHz
ICC
W
23
mA
Table 20:
Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
Parameter/Condition
Symbol
Min
Max
Units
Notes
SCL LOW to SDA data-out valid
tAA
0.2
0.9
s
Time the bus must be free before a new transition can start
tBUF
1.3
s
Data-out hold time
tDH
200
ns
SDA and SCL fall time
tF
300
ns
Data-in hold time
tHD:DAT
0
s
Start condition hold time
tHD:STA
0.6
s
Clock HIGH period
tHIGH
0.6
s
Noise suppression time constant at SCL, SDA inputs
tI50
ns
Clock LOW period
tLOW
1.3
s
SDA and SCL rise time
tR0.3
s
SCL clock frequency
fSCL
400
KHz
Data-in setup time
tSU:DAT
100
ns
Start condition setup time
tSU:STA
0.6
s
Stop condition setup time
tSU:STO
0.6
s
WRITE cycle time
tWRC
10
ms
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT2S3216D-20 | 32K X 16 MULTI DEVICE SRAM MODULE, 20 ns, DMA40 |
| MT46H256M32LFCM-5:A | 256M X 32 DDR DRAM, 5 ns, PBGA90 |
| MT46H256M32L2JV-75IT:A | 256M X 32 DDR DRAM, 6 ns, PBGA168 |
| MT46H256M32L4CM-54IT:A | 256M X 32 DDR DRAM, 5 ns, PBGA90 |
| MT46H256M32L4MC-54AT:A | 256M X 32 DDR DRAM, 5 ns, PBGA240 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT-19 | 功能描述:TERM BARRIER 19CIRC DUAL ROW RoHS:是 類別:連接器，互連式 >> 接線座 - 隔板塊 系列:M 標(biāo)準(zhǔn)包裝:10 系列:Beau™ 38780 端接塊類型:阻隔塊 電路數(shù):15 導(dǎo)線入口數(shù)目:30 間距:0.438"（11.12mm） 行數(shù):2 電流:15A 電壓:300V 線規(guī):14-22 AWG 頂部端子:螺釘 底部端子:焊片 阻擋層類型:雙壁（雙） 特點:法蘭 顏色:黑 包裝:散裝 安裝類型:通孔 工作溫度:- 材料 - 絕緣體:聚對苯二甲酸丁二酯（PBT），玻璃纖維增強型 材料可燃性額定值:UL94 V-0 其它名稱:038780-111538780-1115387801115 |
| MT190A | 制造商:Black Box Corporation 功能描述:SMART 64K CSU/DSU |
| MT190AD130 | 制造商:BLACK BOX 功能描述:64K CSU/DSU |
| MT190A-D48 | 制造商:Black Box Corporation 功能描述:Smart 64K CSU/DSUs, 24 48-VDC |
| MT190A-D48-W1 | 制造商:Black Box Corporation 功能描述:1 YEAR WARRANTY FOR MT190A-D48 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。