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參數(shù)資料
| 型號： | MT312 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 消費家電 |
| 英文描述： | Satellite Channel Decoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | MQFP-80 |
| 文件頁數(shù)： | 13/90頁 |
| 文件大?。?/td> | 318K |
| 代理商： | MT312 |
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Functional Overview
MT312
13
1.4.3 The De-interleaver Block
1.4.3.1 DVB
Before transmission, the data bytes are interleaved
with each other in a cyclic pattern of twelve. This
ensures the bytes are spaced out to avoid the
possibility of a noise spike corrupting a group of
consecutive message bytes. The diagram below
shows conceptually how the convolutional de-
interleaving system works. The synchronisation byte
is always loaded into the First-In-First-Out (FIFO)
memory in branch 0. The switch is operated at
regular byte intervals to insert successively received
bytes into successive branches. After 12 bytes have
been received, byte 13 is written next to the
synchronisation byte in branch 0, etc. In the MT312,
this de-interleaving function is realised using on-chip
Random Access Memory (RAM).
1.4.3.2 DSS
Before transmission, the data bytes are interleaved
with each other in a cyclic pattern of thirteen. This
ensures the bytes are spaced out to avoid the
possibility of a noise spike corrupting a group of
consecutive message bytes. The diagram below
shows conceptually how the convolutional de-
interleaving system works. On the MT312, this
function is realised in the same Random Access
Memory (RAM) as used for DVB, but utilising
different addressing algorithm.
0
1
2
3
4
5
6
7
8
9
10
11
0
1
2
3
4
5
6
7
8
9
10
11
one
byte per
position
17x1
17x2 bytes
17x3 bytes
17x4 bytes
17x5 bytes
17x6 bytes
17x7 bytes
17x8 bytes
17x9 bytes
17x10 bytes
17x11 bytes
Sync word route
Figure 7 - DVB Conceptual diagram o f the conoluntional de-interleaver block
0
1
2
12D
12D
12D
Input
Output
145
Figure 8 - DSS Conceptual diagram of the convolutional de-interleaver block
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