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參數(shù)資料
| 型號： | MT312 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Satellite Channel Decoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | MQFP-80 |
| 文件頁數(shù)： | 18/90頁 |
| 文件大?。?/td> | 318K |
| 代理商： | MT312 |
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MT312
Software Control
18
2 MT312 Software Control
This section describes the sequences of register
operations needed to acquire DVB and DSS
channels with known or unknown parameters.
Communication with the MT312 is via a standard 2-
wire bus and the
fi
rst byte following the chip address,
in write mode, is the register address (RADD).
The register map is organised to group important
Read registers at the lowest addresses, then the
main control Write registers in the next block of
addresses.
The
fi
rst register to be written must be the
Con
fi
guration register, which has been placed at the
highest register address, because it is only written
once during the initialisation sequence.
The CONFIG register can only be reset by the
hardware reset. The MT312 is held in a power saving
mode following the hardware reset.
After a hardware reset, the MT312 must be taken out
of the power save mode by writing a one to the MSB
of the CONFIG register (see 1.1 Introduction). When
MT312 is not being used it can be put back into the
power save mode by writing a zero to the MSB of
CONFIG.
2.1 MT312 Register Map Overview
All write / read registers take on default values on full software reset, except for the con
fi
guration register (127),
that is only reset to the default value by a hardware reset.
Address
Description
Section
Type
00 - 06
Interrupt and Status
5.1to 5.4-
read
07 - 19, 108 - 117, 123, 124
Primary signal monitors
5.5 to 5.17
read
20 - 39, 41, 96, 103
Primary control parameters
4 to 4.20
write / read
40, 42 - 49, 50 - 106, 125
Secondary parameters
11.1.1 to 11.1.52
write / read
107, 118 - 122
Secondary monitors
11.2.1 to 4.22
read
126
Chip identi
fi
cation
5.18
read
127
Chip con
fi
guration
Table 2 - MT312 register map overview
4.22
write / read
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