參數(shù)資料
型號(hào)： MT312
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 消費(fèi)家電
英文描述： Satellite Channel Decoder
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝： MQFP-80
文件頁數(shù)： 47/90頁
文件大小： 318K
代理商： MT312
Forward Error Correction
MT312
47
7 Forward Error Correction
7.1 Forward Error Correction Read/Write Registers
7.1.1 FEC Interrupt Enable. Register 31 (R/W)
When the bits of this register are set high, they enable an event to generate an interrupt on the pin 57. All
interrupts may be enabled together.
B7:
High = Enable DiSEqC
indication on interrupt pin.
B6:
High = Enable Byte Align lock lost indication on interrupt pin.
B5:
High = Enable Byte Align lock indication on interrupt pin.
B4:
High = Enable Viterbi lock lost indication on interrupt pin.
B3:
High = Enable Viterbi lock indication on interrupt pin.
B2:
High = Enable Viterbi BER monitor period reached indication on interrupt pin.
B1:
High = Enable De-scrambler lock lost indication on interrupt pin.
B0:High = Enable De-scrambler lock indication on interrupt pin.
7.1.2 FEC STATUS Output Enable. Register 33 (R/W)
If more than one bit is enabled then the logical-OR combination of the selected status signals will appear on the
STATUS pin 52.
B7-4:
MOCLK RATIO[3:0]
MPEG clock ratio - 6. I.e. range is from 6 to 21
see section 9.1.3 on 54.
B3:
DS lock
High = De-scrambler lock
B2:
BA lock
High = Byte Align lock
B1:
VIT lock
High = Viterbi lock. High = Viterbi lock
NAME
ADR
B7
B6
B5
B4
B3
B2
B1
B0
Def
hex
IE FEC
31
IE FEC[7:0] Interrupt enable FEC
R/W
00
NAME
ADR
B7
B6
B5
B4
B3
B2
B1
B0
Def
hex
FEC STAT EN
33
MOCLK RATIO[3:0]
DS lock
BA
lock
VIT
lock
BER
tog
R/W
14
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