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參數(shù)資料
| 型號： | MT312 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 消費家電 |
| 英文描述： | Satellite Channel Decoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | MQFP-80 |
| 文件頁數(shù)： | 54/90頁 |
| 文件大?。?/td> | 318K |
| 代理商： | MT312 |
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MT312
MPEG Packet Data Output
54
9 MPEG Packet Data Ouput
9.1 MPEG Clock Modes
There are four MOCLK modes of operation, controlled by register bits.
9.1.1 MANUAL MOCLK = 0 and DIS SR = 0.
In this mode MOCLK is generated from the symbol clock . MOCLK will be a continuously running clock once
symbol lock has been achieved in the QPSK block.
9.1.2 MANUAL MOCLK = 0 and DIS SR = 1.
In this mode MOCLK is not generated from the symbol clock but instead uses the data in the QPSK decimation
ratio. This mode is not normally used but is available for engineering test purposes.
9.1.3 MANUAL MOCLK = 1 and DIS SR = 0.
This is the Programmable Clock Division Ratio mode of operation. MOCLK is generated by dividing the PLL
clock frequency by the MOCLK RATIO + 6 see register 33 on 47.
MOCLK frequency =
The range of values of 6 to 9 for (MOCLK RATIO + 6) will guarantee operation for 2 - 45 MSym/s. However, for
a restricted range of symbol rates, higher (MOCLK RATIO + 6) values may be used with a lower MOCLK
frequency. The equation in section 9.4 on 58 must be evaluated to ensure successful operation and avoid
buffer over
fl
ow in the MT312.
MANUAL MOCLK
register 96 bit 7
DIS SR
register 97 bit 7
MOCLK generation mode
0
0
Use Symbol Rate for MOCLK generation.
0
1
Disable use of Symbol Rate for MOCLK generation.
1
0
Manually set MOCLK period from MOCLK RATIO
(reg. 33).
1
1
Use external MICLK (pin 14) signal for MOCLK.
Table 5 - MPEG clock modes
PLL frequency
MOCLK RATIO + 6
MOCLK frequency
comment
60MHz
6
10.0MHz
maximum
60MHz
9
6.667 MHz
minimum
90MHz
6
15MHz
maximum
90MHz
9
10.0MHz
minimum
Table 6 - MOCLK input minimum and maximum frequencies
PLLfrequency
(MCLK_RATIO + 6)
---------------------------------------------------
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