- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359228 > MT312 (ZARLINK SEMICONDUCTOR INC) Satellite Channel Decoder PDF資料下載
參數(shù)資料
| 型號： | MT312 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 消費家電 |
| 英文描述： | Satellite Channel Decoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | MQFP-80 |
| 文件頁數(shù)： | 81/90頁 |
| 文件大?。?/td> | 318K |
| 代理商： | MT312 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁當(dāng)前第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁
Electrical Characteristics
MT312
81
Note 1.8V tolerant pins with thresholds related to 3.3V.
Pin
Name
Description
I/O
Note
V
mA
53
CLK1
2-wire serial bus clock
I
CMOS
5
1
5
1
54
DATA1
2-wire serial bus data
I/O
Open
drain
6
57
IRQ
Active low interrupt output. A low output
on this pin indicates an event has
occurred and the microprocessor should
read the interrupt registers. Reading all
interrupt registers resets this pin.
O
Open
drain
5
1
6
58
MOCLK
MPEG clock output at the data byte rate.
O
CMOS
Tri-
state
3.3
1
69,68,66,65,
64,63,61,59
MDO[7:0]
MPEG transport packet data output bus.
O
CMOS
Tri-
state
3.3
1
71
MDOEN
Logic 1 = MPEG data and clock outputs
disable - Tri-state. Logic 0 = MPEG data
and clock outputs enable
I
CMOS
5
1
72
MOVAL
MPEG data output valid. This pin is high
during the MOCLK clock cycles when
valid data bytes are being output.
O
CMOS
Tri-
state
3.3
1
75
BKERR
Active low uncorrectable block indicator
OR no signal indicator selected by ERR
IND bit 7 of MON CTRL register.
O
CMOS
Tri-
state
3.3
1
76
MOSTRT
MPEG output start signal, high on the
fi
rst byte of a packet.
O
CMOS
Tri-
state
3.3
1
2,9,17,42,50,
55,62,67
CVDD
Core Digital CVDD. All pins must be
connected.
1.8
13,73
VDD
Peripheral VDD. All pins must be
connected.
3.3
37
ADCAVDD
ADC core analogue VDD. All pins must
be connected.
1.8
30
ADCDVDD
ADC core digital VDD. All pins must be
connected.
3.3
25
ADCFVDD
ADC core front end VDD. All pins must
be connected.
3.3
21
PLLVDD
PLL VDD. All pins must be connected.
1.8
1,10,20,41,51,
60,70
CVSS
Digital VSS. All pins must be connected.
0
15,56,74
VSS
Peripheral VSS. All pins must be
connected.
0
36
ADCAGND
ADC core analogue VSS. Must be
connected to analogue GND.
0
31
ADCDGND
ADC core digital VSS. Must be
connected to analogue GND.
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT312T-Y | 2x4mm Rectangular LED Lamps |
| MT3371BN | Wide Dynamic Range DTMF Receiver |
| MT3371BS | Wide Dynamic Range DTMF Receiver |
| MT3371BNR | Wide Dynamic Range DTMF Receiver |
| MT3371BSR1 | Wide Dynamic Range DTMF Receiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT3-1203SI | 制造商:VOLGEN 制造商全稱:VOLGEN 功能描述:3 WATT DC/DC CONVERTER, SIINGLE & MULTIIPLE OUTPUTS |
| MT3-1205SI | 制造商:VOLGEN 制造商全稱:VOLGEN 功能描述:3 WATT DC/DC CONVERTER, SIINGLE & MULTIIPLE OUTPUTS |
| MT3-1212SI | 制造商:VOLGEN 制造商全稱:VOLGEN 功能描述:3 WATT DC/DC CONVERTER, SIINGLE & MULTIIPLE OUTPUTS |
| MT3-1212WI | 制造商:VOLGEN 制造商全稱:VOLGEN 功能描述:3 WATT DC/DC CONVERTER, SIINGLE & MULTIIPLE OUTPUTS |
| MT3-1215WI | 制造商:VOLGEN 制造商全稱:VOLGEN 功能描述:3 WATT DC/DC CONVERTER, SIINGLE & MULTIIPLE OUTPUTS |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。