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參數(shù)資料
| 型號(hào)： | MT312 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Satellite Channel Decoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | MQFP-80 |
| 文件頁數(shù)： | 55/90頁 |
| 文件大小： | 318K |
| 代理商： | MT312 |
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MPEG Packet Data Output
MT312
55
9.1.4 MANUAL MOCLK = 1 and DIS SR = 1.
This is the External MPEG Clock mode of operation. The external MOCLK is input on the MICLK pin 14. The
clock supplied must be a continuous clock, otherwise the data buffers in the MT312 would over
fl
ow and data
would be lost. The maximum permitted MICLK frequency is:
MICLK frequency maximum =
Where PLL frequency is 60MHz the MICLK frequency maximum = 9.524MHz.
Where PLL frequency is 90MHz the MICLK frequency maximum = 14.286MHz.
As in the Programmable Clock Division Ratio mode, the minimum MICLK frequency must be high enough to
clock the complete MPEG packet out before the next one arrives. For this reason, the minimum MICLK
frequency recommended is 6.7MHz at 60MHz and 10MHz at 90MHz.
The MCLKINV control bit in the Output Data Control register (96) will change the phase of the MICLK used to
clock the data out. With MCLKINV = 0, data is clocked out on the positive edge of MICLK. If MCLKINV = 1, data
is clocked out on the negative edge of MICLK.
9.2 Data Output Header Format - DVB only
After decoding the 188 byte MPEG packet, it is output on the MDO pins in 188 consecutive clock cycles.
Additionally, in DVB mode, when the EN TEI bit in the OP CTRL register (96) is set high (default), the TEI bit of
any uncorrectable packet will automatically be set to 1, see 52. If EN TEI bit is low then TEI bit will not be
changed (but note that if this bit is already 1, for example, due to a channel error which has not been corrected,
it will remain high at output).
PLLfrequency
6.3
------------------------------------
0
1
0
0
0
1
1
1
TEI
1st byte
2nd byte
MDO[7]
MDO[0]
Transport
Packet
Header
4 bytes
184 Transport packet bytes
188 byte packet output
Figure 22 - DVB Transport Packet Header bytes
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