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參數(shù)資料
| 型號(hào)： | MT312 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Satellite Channel Decoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | MQFP-80 |
| 文件頁(yè)數(shù)： | 56/90頁(yè) |
| 文件大?。?/td> | 318K |
| 代理商： | MT312 |
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MT312
MPEG Packet Data Output
56
9.3 MPEG/DSS Data Output Signals
MCLKIV=1
MOCLK
MDO7:0
MOSTRT
MOVAL
ERR_IND = 0
BKERR
ERR_IND = 1
BKERR
1st byte packet n
188 (DVB) or 130 (DSS) byte packet n
1st byte packet n+1
Tp
Ti
Figure 23 - MT312 output data wave form diagram
Figure 22 illustrates the case when ERR IND is set
high and the De-scrambler lock remains high. If the
fi
rst packet shown is good, BKERR would remain
high at the
fi
rst MOSTRT shown, going low at the
second MOSTRT shown when that packet has
uncorrected block errors. If the
fi
rst packet shown is
bad, BKERR will go low at the
fi
rst MOSTRT shown
and continue low until a good packed is received.
MOCLK will be a continuously running clock once
symbol lock has been achieved in the QPSK block
and is derived from either the system clock or MICLK
if external clock is selected. MOCLK shown in Figure
24, Figure 25 and Figure 26 with MCLKINV = 1, the
default state, see register 96 in 7.1.3 FEC Set Up.
Register 97 (R/W) on page 51.
MOCLK is the MPEG data byte rate clock, the
internal rate is calculated from the formulae in
section 9.4. The maximum movement in the packet
synchronisation byte position is limited to ± one
output clock period.
All output data and signals (MDO[7:0], MOSTRT,
MOVAL, BKERR) change on the negative edge of
MOCLK (MCLKINV = 1) to present stable data and
signals on the positive edge of the clock.
A complete packet of data is output on MDO[7:0] on
188 (DVB) or 130 (DSS) consecutive clocks and the
MDO[7:0] pins will remain low during the inter packet
gaps.
MOSTRT goes high for the
fi
rst byte clock of a
packet.
MOVAL goes high on the
fi
rst byte of a packet and
remains high until the 188th byte (DVB) or 130th byte
(DSS) has been clocked out.
BKERR has two modes of operation, selected by
ERR IND bit 7 of MON CTRL register 103, see 59.
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| MT3-1212SI | 制造商:VOLGEN 制造商全稱:VOLGEN 功能描述:3 WATT DC/DC CONVERTER, SIINGLE & MULTIIPLE OUTPUTS |
| MT3-1212WI | 制造商:VOLGEN 制造商全稱:VOLGEN 功能描述:3 WATT DC/DC CONVERTER, SIINGLE & MULTIIPLE OUTPUTS |
| MT3-1215WI | 制造商:VOLGEN 制造商全稱:VOLGEN 功能描述:3 WATT DC/DC CONVERTER, SIINGLE & MULTIIPLE OUTPUTS |
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