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參數(shù)資料
| 型號(hào)： | MT46V128M4P-75ZLIT:C |
| 元件分類： | DRAM |
| 英文描述： | 128M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | 0.400 INCH, LEAD FREE, PLASTIC, TSOP-66 |
| 文件頁數(shù)： | 15/94頁 |
| 文件大?。?/td> | 4179K |
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
22
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Commands
DESELECT
The DESELECT function (CS# HIGH) prevents new commands from being executed by
the DDR SDRAM. The DDR SDRAM is effectively deselected. Operations already in
progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to instruct the selected DDR SDRAM to
perform a NOP (CS# is LOW with RAS#, CAS#, and WE# are HIGH). This prevents
unwanted commands from being registered during idle or wait states. Operations
already in progress are not affected.
LOAD MODE REGISTER
The mode registers are loaded via inputs A0–A12. See mode register descriptions in
"Register Definition" on page 15. The LOAD MODE REGISTER command can only be
issued when all banks are idle, and a subsequent executable command cannot be issued
until tMRD is met.
ACTIVE
The ACTIVE command is used to open (or activate) a row in a particular bank for a sub-
sequent access. The value on the BA0, BA1 inputs selects the bank, and the address pro-
vided on inputs A0–A12 selects the row. This row remains active (or open) for accesses
until a precharge command is issued to that bank. A PRECHARGE command must be
issued before opening a different row in the same bank.
READ
The READ command is used to initiate a burst read access to an active row. The value on
the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–Ai (where i
= 9 for x16; 9, 11 for x8; or 9, 11, 12 for x4) selects the starting column location. The value
on input A10 determines whether or not auto precharge is used. If auto precharge is
selected, the row being accessed will be precharged at the end of the READ burst; if auto
precharge is not selected, the row will remain open for subsequent accesses.
WRITE
The WRITE command is used to initiate a burst write access to an active row. The value
on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–Ai
(where i = 9 for x16; 9, 11 for x8; or 9, 11, 12 for x4) selects the starting column location.
The value on input A10 determines whether or not auto precharge is used. If auto pre-
charge is selected, the row being accessed will be precharged at the end of the WRITE
burst; if auto precharge is not selected, the row will remain open for subsequent
accesses. Input data appearing on the DQ is written to the memory array subject to the
DM input logic level appearing coincident with the data. If a given DM signal is regis-
tered LOW, the corresponding data will be written to memory; if the DM signal is regis-
tered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be
executed to that byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row access a
specified time (tRP) after the precharge command is issued, except in the case of concur-
rent auto precharge. With concurrent auto precharge, a READ or WRITE command to a
different bank is allowed as long as it does not interrupt the data transfer in the current
bank and does not violate any other timing parameters. Input A10 determines whether
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PDF描述 |
|---|---|
| MT46V64M4TG-75E | 64M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| MT46V64M4FG-75Z | 64M X 4 DDR DRAM, 0.75 ns, PBGA60 |
| MT47H128M8HQ-3AT | 128M X 8 DDR DRAM, 0.4 ns, PBGA60 |
| MT47H64M16HR-3IT | 64M X 16 DDR DRAM, 0.4 ns, PBGA84 |
| MT48H8M16LFB4-8IT:JTR | 8M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT46V128M4T67A3WC1 | 制造商:Micron Technology Inc 功能描述:128MX4 DDR SDRAM DIE-COM COMMERCIAL 2.5V - Trays |
| MT46V128M4TG-5B/D | 制造商:Samsung Semiconductor 功能描述: |
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