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參數(shù)資料
| 型號： | MT46V128M4P-75ZLIT:C |
| 元件分類： | DRAM |
| 英文描述： | 128M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | 0.400 INCH, LEAD FREE, PLASTIC, TSOP-66 |
| 文件頁數(shù)： | 7/94頁 |
| 文件大?。?/td> | 4179K |
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09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
15
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Register Definition
Mode Register
The mode register is used to define the specific mode of operation of the DDR SDRAM.
This definition includes the selection of a burst length, a burst type, a CAS latency and
an operating mode, as shown in Figure 7 on page 16. The mode register is programmed
via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the
stored information until it is programmed again or the device loses power (except for bit
A8, which is self-clearing).
Reprogramming the mode register will not alter the contents of the memory, provided it
is performed correctly. The mode register must be loaded (reloaded) when all banks are
idle and no bursts are in progress, and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these requirements will result in
unspecified operation.
Mode register bits A0–A2 specify the burst length, A3 specifies the type of burst (sequen-
tial or interleaved), A4–A6 specify the CAS latency, and A7–A12 specify the operating
mode.
Burst Length
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length
being programmable, as shown in Figure 7 on page 16. The burst length determines the
maximum number of column locations that can be accessed for a given READ or WRITE
command. BL = 2, BL = 4, or BL = 8 locations are available for both the sequential and the
interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a boundary is reached. The block is
uniquely selected by A1-Ai when BL = 2, by A2–Ai when BL = 4 and by A3–Ai when BL = 8
(where Ai is the most significant column address bit for a given configuration). The
remaining (least significant) address bit(s) is (are) used to select the starting location
within the block. The programmed burst length applies to both READ and WRITE
bursts.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type
and the starting column address, as shown in Table 4 on page 17.
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| MT46V64M4FG-75Z | 64M X 4 DDR DRAM, 0.75 ns, PBGA60 |
| MT47H128M8HQ-3AT | 128M X 8 DDR DRAM, 0.4 ns, PBGA60 |
| MT47H64M16HR-3IT | 64M X 16 DDR DRAM, 0.4 ns, PBGA84 |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT46V128M4T67A3WC1 | 制造商:Micron Technology Inc 功能描述:128MX4 DDR SDRAM DIE-COM COMMERCIAL 2.5V - Trays |
| MT46V128M4TG-5B/D | 制造商:Samsung Semiconductor 功能描述: |
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