參數(shù)資料
型號(hào)： MT46V128M4P-75ZLIT:C
元件分類(lèi)： DRAM
英文描述： 128M X 4 DDR DRAM, 0.75 ns, PDSO66
封裝： 0.400 INCH, LEAD FREE, PLASTIC, TSOP-66
文件頁(yè)數(shù)： 18/94頁(yè)
文件大?。?/td> 4179K
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
25
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Operations
Bank/Row Activation
Before any READ or WRITE commands can be issued to a bank within the DDR SDRAM,
a row in that bank must be “opened.” This is accomplished via the ACTIVE command,
which selects both the bank and the row to be activated, as shown in Figure 10 on
After a row is opened with an ACTIVE command, a READ or WRITE command may be
issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
entered. For example, a tRCD specification of 20ns with a 133 MHz clock (7.5ns period)
results in 2.7 clocks rounded to 3. This is reflected in Figure 11 on page 26, which covers
any case where 2 < tRCD (MIN)/tCK ≤ 3. (Figure 11 also shows the same case for tRCD;
the same procedure is used to convert other specification limits from time units to clock
cycles.)
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been “closed” (precharged). The minimum time inter-
val between successive ACTIVE commands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to different banks is defined by
tRRD.
Figure 10:
Activating a Specific Row in a Specific Bank
CS#
WE#
CAS#
RAS#
CKE
A0-A12
RA
RA = Row address
BA = Bank address
HIGH
BA0, BA1
BA
CK
CK#
DON’T CARE
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT46V128M4T67A3WC1 制造商:Micron Technology Inc 功能描述:128MX4 DDR SDRAM DIE-COM COMMERCIAL 2.5V - Trays
MT46V128M4TG-5B/D 制造商:Samsung Semiconductor 功能描述:
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