參數(shù)資料
型號(hào)： MT46V128M4P-75ZLIT:C
元件分類(lèi)： DRAM
英文描述： 128M X 4 DDR DRAM, 0.75 ns, PDSO66
封裝： 0.400 INCH, LEAD FREE, PLASTIC, TSOP-66
文件頁(yè)數(shù)： 6/94頁(yè)
文件大?。?/td> 4179K
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
14
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Functional Description
The 512Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory con-
taining 536,870,912 bits. The 512Mb DDR SDRAM is internally configured as a quad-
bank DRAM.
The 512Mb DDR SDRAM uses a double data rate architecture to achieve high-speed
operation. The double data rate architecture is essentially a 2n-prefetch architecture,
with an interface designed to transfer two data words per clock cycle at the I/O pins. A
single read or write access for the 512Mb DDR SDRAM consists of a single 2n-bit wide,
one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit
wide, one-half-clock-cycle data transfers at the I/O pins.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select
the bank; A0–A12 select the row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column location for the burst access.
Prior to normal operation, the DDR SDRAM must be initialized. The following sections
provide detailed information covering device initialization, register definition, com-
mand descriptions, and device operation.
Initialization
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational
procedures other than those specified may result in undefined operation. Power must
first be applied to VDD and VDDQ simultaneously, and then to VREF (and to the system
VTT). VTT must be applied after VDDQ to avoid device latch-up, which may cause perma-
nent damage to the device. VREF can be applied any time after VDDQ but is expected to
be nominally coincident with VTT. Except for CKE, inputs are not recognized as valid
until after VREF is applied. CKE is an SSTL_2 input but will detect an LVCMOS LOW level
after VDD is applied. After CKE passes through VIH, it will transition to a SSTL 2 signal
and remain as such until power is cycled. Maintaining an LVCMOS LOW level on CKE
during power-up is required to ensure that the DQ and DQS outputs will be in the High-
Z state, where they will remain until driven in normal operation (by a read access). After
all power supply and reference voltages are stable, and the clock is stable, the DDR
SDRAM requires a 200s delay prior to applying an executable command.
Once the 200s delay has been satisfied, a DESELECT or NOP command should be
applied, and CKE should be brought HIGH. Following the NOP command, a PRE-
CHARGE ALL command should be applied. Next a LOAD MODE REGISTER command
should be issued for the extended mode register (BA1 LOW and BA0 HIGH) to enable the
DLL, followed by another LOAD MODE REGISTER command to the mode register (BA0/
BA1 both LOW) to reset the DLL and to program the operating parameters. Two-hun-
dred clock cycles are required between the DLL reset and any READ command. A PRE-
CHARGE ALL command should then be applied, placing the device in the all banks idle
state.
Once in the idle state, two AUTO REFRESH cycles must be performed (tRFC must be sat-
isfied.) Additionally, a LOAD MODE REGISTER command for the mode register with the
reset DLL bit deactivated (i.e., to program operating parameters without resetting the
DLL) is required. Following these requirements, the DDR SDRAM is ready for normal
operation.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT46V128M4T67A3WC1 制造商:Micron Technology Inc 功能描述:128MX4 DDR SDRAM DIE-COM COMMERCIAL 2.5V - Trays
MT46V128M4TG-5B/D 制造商:Samsung Semiconductor 功能描述:
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