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參數(shù)資料
| 型號： | MT55L256L32FT-12 |
| 元件分類： | SRAM |
| 英文描述： | 256K X 32 ZBT SRAM, 9 ns, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 15/25頁 |
| 文件大小： | 300K |
| 代理商： | MT55L256L32FT-12 |
22
8Mb: 512K x 18, 256K x 32/36 Flow-Through ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L512L18F_C.p65 – Rev. 2/02
2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
FLOW-THROUGH ZBT SRAM
NOP, STALL, AND DESELECT CYCLES
READ
Q(A3)
456
789
10
A3
A4
A5
D(A4)
123
CLK
CE#
R/W#
CKE#
BWx#
ADV/LD#
ADDRESS
DQ
COMMAND
WRITE
D(A4)
STALL
WRITE
D(A1)
READ
Q(A2)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
tKHQZ
A1
A2
Q(A2)
D(A1)
Q(A3)
tKHQX
Q(A5)
NOTE: 1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CKE# being used to create a “ pause.” A WRITE is not
performed during this cycle.
2. For this waveform, ZZ and OE# are tied LOW.
3. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1.
4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most
recent data may be from the input data register.
NOP, STALL, AND DESELECT TIMING PARAMETERS
-10
-11
-12
SYM
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
tKHQX
3.0
ns
tKHQZ
5.0
ns
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PDF描述 |
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| MT55L512V18PF-6 | 512K X 18 ZBT SRAM, 3.5 ns, PBGA165 |
| MT57W4MH9CF-6 | 4M X 9 DDR SRAM, 0.5 ns, PBGA165 |
| MT58L128L36D1T-5IT | 128K X 36 STANDARD SRAM, 2.8 ns, PQFP100 |
| MT58L128V36P1B-4 | 128K X 36 STANDARD SRAM, 2.3 ns, PBGA119 |
| MT58L32L36PT-7.5 | 32K X 36 CACHE SRAM, 4.2 ns, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT55L256L32FT-12IT | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT55L256L32P | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:8Mb ZBT SRAM |
| MT55L256L32PF-10 | 制造商:Micron Technology Inc 功能描述: |
| MT55L256L32PT10 | 制造商:MICRON 功能描述:* |
| MT55L256L32PT-10 | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Quad 3.3V 8M-Bit 256K x 32 5ns 100-Pin TQFP 制造商:Micron Technology Inc 功能描述: |
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