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參數(shù)資料
| 型號： | MT55L256L32FT-12 |
| 元件分類： | SRAM |
| 英文描述： | 256K X 32 ZBT SRAM, 9 ns, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 25/25頁 |
| 文件大?。?/td> | 300K |
| 代理商： | MT55L256L32FT-12 |
9
8Mb: 512K x 18, 256K x 32/36 Flow-Through ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L512L18F_C.p65 – Rev. 2/02
2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
FLOW-THROUGH ZBT SRAM
FBGA PIN DESCRIPTIONS
x18
x32/x36
SYMBOL
TYPE
DESCRIPTION
6R
SA0
Input
Synchronous Address Inputs: These inputs are registered and must
6P
SA1
meet the setup and hold times around the rising edge of CLK.
2A, 9A, 2B,
S A
3P, 3R, 4P, 4R, 3P, 3R, 4P, 4R,
8P, 8R, 9P, 9R,
8P, 8R, 9P,
10A, 10B, 10P, 9R, 10A, 10B,
10R, 11A, 11R 10P, 10R, 11R
5B
BWa#
Input
Synchronous Byte Write Enables: These active LOW inputs allow
4A
5A
BWb#
individual bytes to be written and must meet the setup and hold
–
4A
BWc#
times around the rising edge of CLK. A byte write enable is LOW
–
4B
BWd#
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQa’s and DQPa; BWb# controls DQb’s and DQPb.
For the x32 and x36 versions, BWa# controls DQa’s and DQPa; BWb#
controls DQb’s and DQPb; BWc# controls DQc’s and DQPc; BWd#
controls DQd’s and DQPd. Parity is only available on the x18 and x36
versions.
7A
CKE#
Input
Synchronous Clock Enable: This active LOW input permits CLK to
propogate throughout the device. When CKE# is HIGH, the device
ignores the CLK input and effectively internally extends the
previous CLK cycle. This input must meet the setup and hold times
around the rising edge of CLK.
7B
R/W#
Input
Read/Write: This input determines the cycle type when ADV/LD# is
LOW and is the only means for determining READs and WRITEs.
READ cycles may not be converted into WRITEs (and vice versa)
other than by loading a new address. A LOW on this pin permits
BYTE WRITE operations to meet the setup and hold times around
the rising edge of CLK. Full bus-width WRITEs occur if all byte write
enables are LOW.
6B
CLK
Input
Clock: This signal registers the address, data, chip enable, byte write
enables, and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock’s rising
edge.
3A
CE#
Input
Synchronous Chip Enable: This active LOW input is used to enable
the device. CE# is sampled only when a new external address is
loaded. (ADV/LD# is LOW)
6A
CE2#
Input
Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded.
11H
ZZ
Input
Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.
3B
CE2
Input
Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded.
8B
OE#(G#)
Input
Output Enable: This active LOW, asynchronous input enables the
data I/O output drivers.
(continued on next page)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT55L256L32FT-12IT | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT55L256L32P | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:8Mb ZBT SRAM |
| MT55L256L32PF-10 | 制造商:Micron Technology Inc 功能描述: |
| MT55L256L32PT10 | 制造商:MICRON 功能描述:* |
| MT55L256L32PT-10 | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Quad 3.3V 8M-Bit 256K x 32 5ns 100-Pin TQFP 制造商:Micron Technology Inc 功能描述: |
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