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6437E–ATARM–23-Apr-13
SAM9M11
Enable the PDC in transmission and reception to start the processing (TDES_PTCR).
When the processing completes, the bit ENDRX (or RXBUFF) in the TDES Interrupt Status
Register (TDES_ISR) raises. If an interrupt has been enabled by setting the corresponding
bit in TDES_IER, the interrupt line of the TDES is activated.
45.4.3
Last Output Data Mode
This mode is used to generate cryptographic checksums on data (MAC) using a CBC or a CFB
encryption algorithm (See FIPS Publication 81 Appendix F).
After each end of encryption/decryption, the output data is available either on the output data
registers for Manual and Auto mode or at the address specified in the receive buffer pointer for
The Last Output Data bit (LOD) in the TDES Mode Register (TDES_MR) retrieves only the last
data of several encryption/decryption processes.
Therefore, there is no need to define a read buffer in PDC mode.
This data is only available on the Output Data Registers (TDES_ODATAxR).
45.4.3.1
Manual and Auto Modes
If LOD = 0:
The DATRDY flag is cleared when at least one of the Output Data Registers is read. See
FigureFigure 45-1. Manual and Auto Modes with LOD = 0
If the user does not want to read the output data registers between each encryption/decryption,
the DATRDY flag will not be cleared. If the DATRDY flag is not cleared, the user will not be
informed of the end of the encryptions/decryptions that follow.
If LOD = 1:
The DATRDY flag is cleared when at least one Input Data Register is written, before the start of
a new transfer. See
Figure 45-2. No further Output Data Register reads are necessary between
consecutive encryptions/decryptions.
Encryption or Decryption Process
Read the TDES_ODATAxR
Write START bit in TDES_CR (Manual mode)
DATRDY
Write TDES_IDATAxR register(s) (Auto mode)
or