国偷自产一区二区三区蜜臀,男男腐大尺度无码激情av

您好，
買(mǎi)賣(mài)IC網(wǎng)歡迎您。
請(qǐng)登錄
免費(fèi)注冊(cè)

您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄25633 > MT80C31-25R (TEMIC SEMICONDUCTORS) 8-BIT, 25 MHz, MICROCONTROLLER, PQFP44 PDF資料下載

型號(hào)：	MT80C31-25R
廠商：	TEMIC SEMICONDUCTORS
元件分類(lèi)：	微控制器/微處理器
英文描述：	8-BIT, 25 MHz, MICROCONTROLLER, PQFP44
文件頁(yè)數(shù)：	127/1447頁(yè)
文件大?。?/td>	3788K
代理商：	MT80C31-25R

6437E–ATARM–23-Apr-13

46. Secure Hash Algorithm (SHA)

Description

The Secure Hash Algorithm (SHA) is compliant with the American FIPS (Federal Information

Processing Standard) Publication 180-2 specification.

The 512-bit block of message is stored in 16 x 32-bit registers (SHA_IDATAxR) which are all

write-only, by software or through PDC channels.

As soon as the input data (512-bit block) is written, the hash processing may be started. The

registers comprising the 512-bit block of a padded message must be entered consecutively.

Then the message digest is ready to be read out on the 5 up to 8 x 32-bit output data registers

(SHA_ODATAxR), by software only.

Embedded Characteristics

Supports Secure Hash Algorithm (SHA1 and SHA256)

Compliant with FIPS Publication 180-2

Configurable Processing Period:

– 85 Clock Cycles to Maximize the Bandwidth for SHA1 or 386 Clock Cycles or Other

Applications in PDC (Peripheral DMA)

– 72 Clock Cycles to Maximize the Bandwidth for SHA256 or 265 Clock Cycles or

Other Applications in PDC (Peripheral DMA)

Connection to PDC Channel Capabilities Optimizes Data Transfers

– One Channel for the Transmitter

– Next Buffer Support

Product Dependencies

Power Management

The SHA may be clocked through the Power Management Controller (PMC), so the programmer

must first configure the PMC to enable the SHA clock.

Interrupt

The SHA interface has an interrupt line connected to the Advanced Interrupt Controller (AIC).

Handling the SHA interrupt requires programming the AIC before configuring the SHA.

Functional Description

The Secure Hash Algorithm (SHA) module requires a padded message according to FIPS180-2

specification. The first block of the message must be indicated to the module. The SHA module

produces a 160-bit message digest each time a block is written in SHA1 mode or a 256-bit mes-

sage digest each time a block is written in SHA256 mode.

SHA Algorithm

The module can process SHA1 or SHA256 by means of a configuration bit.

相關(guān)PDF資料	PDF描述
MQ80C52TXXX-16/883	8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44
MR80C52EXXX-20SCD	8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQCC44
MR80C32-16SHXXX	8-BIT, 16 MHz, MICROCONTROLLER, CQCC44
MD80C32EXXX-30/883	8-BIT, 30 MHz, MICROCONTROLLER, CDIP40
MR80C32E-16SC	8-BIT, 16 MHz, MICROCONTROLLER, CQCC44

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
MT80C31BH	制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Intel 功能描述:
MT80C51BH	制造商:ROCHESTER 制造商全稱(chēng):ROCHESTER 功能描述:CMOS SINGLE - CHIP 8-BIT MICROCOMPUTER 64K program Memory Space
MT80C51FB	制造商:Rochester Electronics LLC 功能描述:- Bulk
MT80C51FB/B	制造商:Intel 功能描述:
MT80GB	制造商:Datak Corporation 功能描述:

發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

*型號(hào)	*數(shù)量	廠商	批號(hào)	封裝

采購(gòu)需求

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

我的聯(lián)系方式

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)