1073
6437E–ATARM–23-Apr-13
SAM9M11
Warning: In DMA mode, reading to the Output Data registers before the last data transfer may lead to unpredictable result.
44.4.4
Security Features
44.4.4.1
Countermeasures
The AES also features hardware countermeasures that can be useful to protect data against Dif-
ferential Power Analysis (DPA) attacks.
These countermeasures can be enabled through the CTYPE field in the AES Mode Register.
This field is write-only, and all changes to it are taken into account if, at the same time, the Coun-
Note:
Enabling countermeasures has an impact on the AES encryption/decryption throughput.
By default, all the countermeasures are enabled.
The best throughput is achieved with all the countermeasures disabled. On the other hand, the
best protection is achieved with all of them enabled.
The LOADSEED bit in the AES Control Register (AES_CR) restarts the countermeasures gen-
erator to an internal pre-defined value.
44.4.4.2
Unspecified Register Access Detection
When an unspecified register access occurs, the URAD bit in the Interrupt Status Register
(AES_ISR) raises. Its source is then reported in the Unspecified Register Access Type field
(URAT). Only the last unspecified register access is available through the URAT field.
Several kinds of unspecified register accesses can occur:
Input Data Register written during the data processing when SMOD=IDATAR0_START
Output Data Register read during data processing
Mode Register written during data processing
Output Data Register read during sub-keys generation
Mode Register written during sub-keys generation
Write-only register read access
The URAD bit and the URAT field can only be reset by the SWRST bit in the AES_CR control
register.