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6437E–ATARM–23-Apr-13
SAM9M11
44.4.2.3
DMA Mode
The DMA Controller can be used in association with the AES to perform an encryption/decryp-
tion of a buffer without any action by the software during processing.
The SMOD field of the AES_MR must be set either to 0x1 or 0x2 depending on how the DMA is
configured.
The start address of any transfer descriptor must be set to AES_IDATAR0 register.
The DMA chunk size can be set either to single data or to 4 data per request.
If the entire AES message to be processed requires only a single DMA transfer descriptor, or
if the message is transferred using several DMA transfer descriptors which sizes are greater
than 128 bits (4 words), the DMA must be configured with non incremental addresses. Then,
the SMOD field of the AES_MR register must be set to 0x2.
If the AES message is described using DMA transfer descriptors having a transfer size equal
to 128 bits (4 words), the DMA must be configured to perform non incremental addresses.
Then, the SMOD field of the AES_MR register must be set to 0x1.
When DMA is used, the type of data transfer (byte, half-word or word) depends on the operation
mode.
44.4.3
Last Output Data Mode
This mode is used to generate cryptographic checksums on data (MAC) by means of cipher
block chaining encryption algorithm (CBC-MAC algorithm for example).
After each end of encryption/decryption, the output data is available either on the output data
registers for Manual and Auto mode or at the address specified in the receive buffer pointer for
The Last Output Data bit (LOD) in the AES Mode Register (AES_MR) allows retrieval of only the
last data of several encryption/decryption processes.
Therefore, there is no need to define a read buffer in DMA mode.
This data is only available on the Output Data Registers (AES_ODATARx).
Table 44-3.
Data Transfer Type for the Different Operation Modes
Operation Mode
Data Transfer Type
ECB
Word
CBC
Word
OFB
Word
CFB 128-bit
Word
CFB 64-bit
Word
CFB 32-bit
Word
CFB 16-bit
Half-word
CFB 8-bit
Byte
CTR
Word