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參數(shù)資料
| 型號： | MT90220 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Octal IMA/UNI PHY Device(八端口 IMA/UNI 物理層設(shè)備（八端口ATM IMA和UNI處理器）) |
| 中文描述： | 八路IMA的/單向物理層設(shè)備（八端口IMA的/單向物理層設(shè)備（八端口自動柜員機(jī)IMA的和單向處理器）） |
| 文件頁數(shù)： | 14/118頁 |
| 文件大?。?/td> | 310K |
| 代理商： | MT90220 |
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MT90220
6
81,88, 90,
97,99,107,
109,116
DSTo
[7:0]
O
Serial PCM Data Output 7-0
. A 1.544 Mbit/s or 2.048 Mbps serial stream which
contain 24 (T1) or 32 (E1) PCM or data channels received on T1 or E1 line. The
output is set to high impedance for unused channels and if the link is not used.
118, 124,
127, 134,
136, 143,
145, 151
DSTi
[7:0]
I
Serial PCM Data Input 7-0
. A 1.544 Mbit/s or 2.048 Mbps serial stream which
contains the 24 (T1) or 32 (E1) PCM or data channels on T1 or E1 line.
83, 85, 92,
94, 101,
103, 111,
113
TXCKi/o
[7:0]
I/O
PCM Interface Transmit Clock 7-0.
This pin is an input for PCM Modes 2, 4, 5 and
7. It is an output for Interface Modes 1, 3, 6 and 8 (see Section 4.2, PCM System
Interface Modes).
It is the clock for serial PCM data transmission of the T1 and E1 framers. The TXCK
source is software selectable and can be either one of the eight RXCK or one of the
four REFCK signals. It is used for internal transmit timing and should be connected
to the Transmit Clock of the framer.
1. The TXCK is 4.096 MHz for ST-BUS applications.
2. For generic PCM Interfaces (non ST-BUS or asynchronous line termination),
these outputs can be programmed to provide either a 1.544 MHz (T1) or 2.048
MHz (T1 or E1) clock.
80, 87, 89,
96, 98,
106, 108,
115
TXSYNCio
[7:0]
I/O
Transmit Line 8KHz Frame Pulse 7-0
. This pin is an input for Interface Modes 2,
4, 5 and 7. It is an output for Interface Modes 1, 3, 6 and 8 (see PCM Section 4.2,
PCM System Interface Modes).
It is the 8 kHz reference used as transmit synchronization for the PCM system
interface. When an output, the TXSYNC is generated from the TXCK signal and is
independent from other TXSYNC signals. Two output modes can be programmed:
1. For ST-BUS applications, it is a low going pulse (F0), that delimits the 32 channel
frame of the ST-BUS interface at DSTi and DSTo lines (see Figure 25 - ST-BUS
Timing Diagram for this sync pulse). The frame pulse is typically received through
the RXSYNC[0] pin.
2. For generic PCM Interfaces, it can be programmed to generate either a positive
or negative pulse polarity that lines up with the first bit of the PCM system interface.
117, 125,
126, 133,
135, 142,
144, 150
RXSYNCi
[7:0]
I
Receive line 8KHz Frame Pulse 7-0
. This signal represents the 8 KHz reference
received from the incoming T1 or E1 line. The MT90220 can be programmed to
accept different 8 KHz pulse formats at this input.
1. For ST-BUS applications, it is a low going pulse (F0), which delimits the 32
channel frame of ST-BUS interface at DSTi and DSTo lines. See STBUS timing
diagram for this sync pulse.
2. For generic PCM Interfaces, it can be programmed to accept either positive or
negative pulse polarities.
120, 122,
129, 131,
138, 140,
146, 148
RXCKi
[7:0]
I
PCM Interface Receive Clock 7-0.
This input line represents the clock for the
receive serial PCM data of the T1 and E1 framers. The T1 or E1 frequency value to
be received at this input clock is defined by the user through an internal register.
1. For ST-BUS applications, input pin RXCKi receives the 4.096 MHz signal.
2. For generic PCM Interfaces, these inputs can be programmed to accept either a
1.544 MHz (T1) or 2.048 MHz (T1 or E1) clock.
154, 155
PLLREF
[1:0]
O
Output reference to an external PLL
. See 4.3 Description of the PCM Interface
for details.
158, 159,
160, 161
REFCK
[3:0]
I
Input reference clock inputs 3 to 0.
Receive the de-jittered transmit clock
reference to be internally routed to the T1/E1 framer transmit clocks (output pins
TXCK[7:0]. See “Description of the PCM Interface” on page 23. for more details.
System Signals
Pin Description (continued)
Pin #
Name
I/O
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90221 | Quad IMA/UNI PHY Device(四端口 IMA/UNI 物理層設(shè)備（四端口ATM IMA和UNI處理器）) |
| MT90401 | SONET/SDH System Synchronizer(SONET/SDH 系統(tǒng)同步裝置（由一個數(shù)字鎖相環(huán)組成）) |
| MT9040 | T1/E1 Synchronizer(T1/E1 系統(tǒng)同步裝置（由一個數(shù)字鎖相環(huán)組成）) |
| MT9041A | () |
| MT9041B | T1/E1 System Synchronizer(T1/E1系統(tǒng)同步裝置（由一個數(shù)字鎖相環(huán)組成）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90220AL | 制造商:Zarlink Semiconductor Inc 功能描述:I.C. |
| MT90220ALX01 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90221 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device |
| MT90221AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device |
| MT90222 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:4/8/16 Port IMA/TC PHY Device |
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