參數(shù)資料
型號(hào): MT90220
廠商: Mitel Networks Corporation
英文描述: Octal IMA/UNI PHY Device(八端口 IMA/UNI 物理層設(shè)備(八端口ATM IMA和UNI處理器))
中文描述: 八路IMA的/單向物理層設(shè)備(八端口IMA的/單向物理層設(shè)備(八端口自動(dòng)柜員機(jī)IMA的和單向處理器))
文件頁數(shù): 87/118頁
文件大小: 310K
代理商: MT90220
MT90220
79
8.0 Application Notes
Inverse Multiplexing for ATM (IMA) divides a high-
bandwidth stream of ATM cells in a round-robin
fashion and sends them over grouped T1/E1 lines in
a logical connection (on public or private networks)
and recombines the cells to recover the original high-
bandwidth stream at the receiving end. MITEL’s
MT90220 is ideally suited to implement the IMA
function.
8.1
Connecting the MT90220 to Various T1/E1
Framers
Many off-the-shelf T1/E1 framers require the
generation of a 1.544 MHz (T1) or 2.048 MHz (E1)
transmit clock reference signal at an input pin. The
MT9042 can generate both these clocks and the ST-
BUS back-plane signals (C4,F0). Figure 19 provides
an example of PCM Modes 2 and 4 in an IMA
implementation using existing T1/E1 framers and a
common 2 Mbps ST-Bus backplane.
New generation MITEL framers only require the ST-
BUS 4.096 MHz (C4) clock and a Frame Pulse (F0i)
at the transmit interface. An internal PLL generates
the required 1.544 MHz (T1) or 2.048 MHz (E1)
transmit clock. Figure 20 provides an example of
PCM Modes 2 and 4 in an IMA implementation
based on the MITEL MT90220 and the MITEL
MT9074 framers. This configuration supports CTC
mode. Although the MT9074 use the ST-Bus format
but it is not configured as a common backplane.
Figure 21 exemplifies PCM Modes 2 and 4 in an IMA
implementation supporting the asynchronous link
operation mode. Each T1 or E1 framer uses
independent clock and synchronization signals which
corresponds to ITC mode.
Figure 22 exemplifies PCM Modes 1 and 3 in an IMA
implementation supporting the asynchronous link
operation mode. Each T1 or E1 framer uses
independent clock and synchronization signals.
Figure 23 exemplifies PCM Mode 5 and 7 in an IMA
implementation supporting the asynchronous link
operation mode where the TXCLK signal is provided
by the T1 interface. Each T1 framer uses
independent clock and synchronization signals.
相關(guān)PDF資料
PDF描述
MT90221 Quad IMA/UNI PHY Device(四端口 IMA/UNI 物理層設(shè)備(四端口ATM IMA和UNI處理器))
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MT9041A ()
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