- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383644 > MT90220 (Mitel Networks Corporation) Octal IMA/UNI PHY Device(八端口 IMA/UNI 物理層設(shè)備（八端口ATM IMA和UNI處理器）) PDF資料下載
參數(shù)資料
| 型號： | MT90220 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Octal IMA/UNI PHY Device(八端口 IMA/UNI 物理層設(shè)備（八端口ATM IMA和UNI處理器）) |
| 中文描述： | 八路IMA的/單向物理層設(shè)備（八端口IMA的/單向物理層設(shè)備（八端口自動柜員機IMA的和單向處理器）） |
| 文件頁數(shù)： | 83/118頁 |
| 文件大?。?/td> | 310K |
| 代理商： | MT90220 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁當前第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁
MT90220
75
7.11
Interrupt Registers Description
Tables 95 to 103 describe the
Interrupt
registers.
a. Bit 7 is present only for Link 0. In all other Link Status Registers, this bit is set to 0.
b. Bit 6 is present only for Link 0. In all other Link Status Registers, this bit is set to 0.
Address (Hex):
Direct access
Reset Value (Hex):
232
00
Bit #
Type
Description
7:0
R
Each bit represents a link. A ’1’ means that the corresponding link has a valid request for
interrupt. The level of the IRQ pin is controlled by the bits in this register and the
corresponding bits in the IRQ Master Enable Register. A write does not have any affect
on the bits in this register. The status bit is not latched and changing the mask bit in the
IRQ Master Register has a direct effect on the level of the IRQ pin.
Table 95 - IRQ Master Status Register
Address (Hex):
Direct access
Reset Value (Hex):
218
00
Bit #
Type
Description
7:0
R/W
Each bit represents a link. A ’1’ means that the interrupt form the corresponding link is
enabled and that the level of the IRQ pin is low if the corresponding bit in the IRQ Master
Register is set. A ’0’ means that the IRQ level is not affected by the corresponding bit.
Table 96 - IRQ Master Enable Register
Address (Hex):
Direct access
Reset Value (Hex):
222 - 229
1 Status register per link
00
Bit #
7
a
Type
Description
R
A ’1’ in this bit means that at least one of the IRQ sources from the IMA Group Overflow
Status Register is requesting service. This bit can be cleared only by service the source of
the IRQ. This bit is valid only for the IRQ Link 0 Status register and is reading always a 0 for
the IRQ Link 1-7 Status registers.
A 1 in this bit means that at least one of the Ready bit used to initiate a transfer of a TX ICP
cell for at least 1 of the IMA Group is returned to 1 (meaning that the transfer of the TX ICP
cell is complete) or a frame pulse was detected for an IMA Group. This bit is cleared by
writing a 0 to it. This bit is valid only for the IRQ Link 0 Status register and is reading always
a 0 for the IRQ Link 1-7 Status registers.
ICP Cell with changes received. The link has received an ICP cell which contain one or
more changes in it. This status bit can be cleared by writing a ’0’ to it. This bit is set when
an ICP cell is stored in RX ICP cell buffer as defined in RX ICP cell type RAM register 1or 2.
IV. The Link has received an ICP cell which contain a violation as defined in Table 16 of IMA
Spec. This status bit can be cleared by writing a ’0’ to it.
LODS. The Link is Out of Delay Synchronization. This status bit can be cleared by writing a
’0’ to it.
LIF. Loss of IMA Frame. This status bit can be cleared by writing a ’0’ to it.
LCD Loss of Cell Delineation. This status bit can be cleared by writing a ’0’ to it.
Link Counter Overflow Interrupt. One or more counters associated with the link overflowed.
This status bit can be cleared only by reading or writing to the counter(s) which is (are) the
source for the IRQ.
6
b
R/W
5
R/W
4
R/W
3
R/W
2
1
0
R/W
R/W
R
Table 97 - IRQ Link Status Registers
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90221 | Quad IMA/UNI PHY Device(四端口 IMA/UNI 物理層設(shè)備（四端口ATM IMA和UNI處理器）) |
| MT90401 | SONET/SDH System Synchronizer(SONET/SDH 系統(tǒng)同步裝置（由一個數(shù)字鎖相環(huán)組成）) |
| MT9040 | T1/E1 Synchronizer(T1/E1 系統(tǒng)同步裝置（由一個數(shù)字鎖相環(huán)組成）) |
| MT9041A | () |
| MT9041B | T1/E1 System Synchronizer(T1/E1系統(tǒng)同步裝置（由一個數(shù)字鎖相環(huán)組成）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90220AL | 制造商:Zarlink Semiconductor Inc 功能描述:I.C. |
| MT90220ALX01 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90221 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device |
| MT90221AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device |
| MT90222 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:4/8/16 Port IMA/TC PHY Device |
發(fā)布緊急采購，3分鐘左右您將得到回復。