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參數(shù)資料
| 型號： | MT90870 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Flexible 12 k Digital Switch (F12kDX) |
| 中文描述： | 靈活的12畝數(shù)字交換機（F12kDX） |
| 文件頁數(shù)： | 24/86頁 |
| 文件大?。?/td> | 2093K |
| 代理商： | MT90870 |
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MT90870
Data Sheet
24
Zarlink Semiconductor Inc.
purposes of describing the device operation, the remaining part of this document assumes the ST-BUS style frame
pulse with a single width frame pulse of 122 ns and the C8IPOL bit is set to one unless explicitly stated otherwise.
In addition, the device provides FP8o, FP16o, C8o and C16o outputs to support external devices which connect to
the Local port. The Local frame pulses (FP8o, FP16o) will be provided in the same style as the master frame pulse
(FP8i). The polarity of C8o and C16o, at the Frame Boundary, can be controlled by the Control Register bit,
COPOL. An analogue phase lock loop (APLL) is used to multiply the external clock frequency to generate an
internal clock signal operated at 131.072 MHz.
2.4 Backplane Frame Pulse Input and Local Frame Pulse Output Alignment
The MT90870 accepts a Backplane Frame Pulse (FP8i) and generates the Local Frame Pulse outputs, FP8o and
FP16o, which are aligned to the master frame pulse. There is a constant three frame delay for data being switched.
Figure 8, Backplane and Local Frame Pulse Alignment for Data Rates of 2 Mb/s, 4 Mb/s, 8 Mb/s and 16 Mb/s,
shows the backplane and local frame pulse alignment for different data rates.
For further details of Frame Pulse conditions and options see Section 13.1, Control Register (CR), Figure 18,
Frame Boundary Conditions, ST- BUS Operation, and Figure 19, Frame Boundary Conditions, GCI - BUS
Operation.
Figure 8 - Backplane and Local Frame Pulse Alignment for Data Rates of 2 Mb/s, 4 Mb/s, 8 Mb/s
and 16 Mb/s
3.0 Input and Output Offset Programming
3.1 Input Channel Delay Programming (Backplane and Local Input Streams)
Various registers are used to control the input sampling point (delay) and the output advancement for the Local and
Backplane streams. The following sections explain the details of these offset programming features.
The control of the Input Channel Delay and the Input Bit Delay allows each input stream to have a different frame
boundary with respect to the master frame pulse, FP8i. By default, all input streams have channel delay of zero
such that Ch0 is the first channel that appears after the frame boundary.
CH3
CH7
CH0
CH1
CH2
BSTi/BSTo0-31
(16 Mb/s)
C8o
FP8o
LSTi/LSTo0-15
(2 Mb/s)
LSTi/LSTo0-15
(4 Mb/s)
LSTi/LSTo0-15
(8 Mb/s)
LSTi/LSTo0-15
(16 Mb/s)
CH2
CH1
CH0
CH6
CH5
CH4
CH3
CH2
CH0
CH4
CH5
CH10
CH9
CH8
CH11
CH
15
CH
14
CH
13
CH
12
CH
11
CH
10
CH
9
CH
8
CH
7
CH
6
CH
5
CH
4
CH
3
CH
2
CH
1
CH
0
CH
19
CH
18
CH
17
CH
16
CH
23
CH
22
CH
21
CH
20
CH1
CH
3
CH
2
CH
1
CH
0
CH
7
CH
6
CH
5
CH
4
CH
11
CH
10
CH
9
CH
8
CH
15
CH
14
CH
13
CH
12
CH
17
CH
16
CH
21
CH
20
CH
19
CH
18
CH
23
CH
22
FP8i
C8i
CH3
CH7
CH0
CH1
CH2
(2 Mb/s)
BSTi/BSTo0-31
(4 Mb/s)
BSTi/BSTo0-31
(8 Mb/s)
CH2
CH1
CH0
CH6
CH5
CH4
CH3
CH2
CH0
CH4
CH5
CH10
CH9
CH8
CH11
CH1
BSTi/BSTo0-31
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90870AG | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 12K X 12K/8K X 4K 1.8V/3.3V 272BGA - Trays |
| MT90870AG2 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 12K X 12K/8K X 4K 1.8V/3.3V 272BGA - Trays |
| MT90871 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Flexible 8K Digital Switch (F8KDX) |
| MT90871AV | 制造商:Microsemi Corporation 功能描述:FLEXIBLE 8K DIGITAL SWITCH 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F8KDX 196PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F8KDX 196PBGA |
| MT90871AV2 | 制造商:Microsemi Corporation 功能描述:PB FREE FLEXIBLE 8K DIGITAL SWITCH - Bulk 制造商:Microsemi Corporation 功能描述:IC, TDM SWITCH 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F8KDX 196PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F8KDX 196PBGA |
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