參數(shù)資料
型號(hào)： MT90870
廠商： Zarlink Semiconductor Inc.
英文描述： Flexible 12 k Digital Switch (F12kDX)
中文描述： 靈活的12畝數(shù)字交換機(jī)（F12kDX）
文件頁(yè)數(shù)： 46/86頁(yè)
文件大?。?/td> 2093K
代理商： MT90870
MT90870
Data Sheet
46
Zarlink Semiconductor Inc.
Figure 17 - Examples of BER transmission channels
10.0 Memory Built-In-Self-Test (BIST) Mode
As operation of the memory BIST will corrupt existing data, this test must only be performed when the device is
placed “out-of-service” or isolated from live traffic.
The memory BIST mode is enabled through the microprocessor port (Section 13.14, Memory BIST Register).
Internal BIST memory controllers generate the memory test pattern (S-march) and control the memory test. The
memory test result is monitored through the Memory BIST Register when controlled via the microprocessor
interface.
11.0 JTAG Port
The MT90870 JTAG interface conforms to the Boundary-Scan IEEE 1149.1 standard. The operation of the
boundary-scan circuit shall be controlled by an external Test Access Port (TAP) Controller. JTAG is intended to be
used during the development cycle. The JTAG interface is operational when the MT90870 Core (V
DD
_core) is
powered at typical voltage levels.
11.1 Test Access Port (TAP)
The Test Access Port (TAP) consists of four input pins and one output pin described as follows:
Test Clock Input (TCK)
TCK
provides the clock for the TAP Controller and is independent of any on-chip clock. TCK permits the
shifting of test data into or out of the Boundary-Scan Registers cells, under the control of the TAP
Controller in Boundary-Scan Mode.
Test Mode Select Input (TMS)
The TAP controller uses the logic signals applied to the
TMS
input to control test operations. The
TMS
signals are sampled at the rising edge of the
TCK
pulse. This pin in internally pulled to V
DD_IO
when not
driven from an external source.
frame boundary
0
1
2
......
.....
254
3
.....
.....
255
0
1
2
......
.....
254
3
.....
.....
255
0
1
2
......
.....
254
3
.....
.....
255
0
1
Channels containing data (traffic)
Channels containing PRBS sequence
Start Ch=0
Length=256
Start Ch=0
Length=3
Start Ch=254
Length=4
0
0
1
1
FP8i
FP
stream
Once Started BER transmission continues until stopped by the BER control register:
2
2
2
Note: Length = Start Chan. + No. of Consecutive channels
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