- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359235 > MT90870 (Zarlink Semiconductor Inc.) Flexible 12 k Digital Switch (F12kDX) PDF資料下載
參數(shù)資料
| 型號： | MT90870 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Flexible 12 k Digital Switch (F12kDX) |
| 中文描述： | 靈活的12畝數(shù)字交換機(jī)（F12kDX） |
| 文件頁數(shù)： | 55/86頁 |
| 文件大?。?/td> | 2093K |
| 代理商： | MT90870 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁當(dāng)前第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁
MT90870
Data Sheet
55
Zarlink Semiconductor Inc.
13.3 Bit Error Rate Test Control Register (BERCR)
Address 0002h.
The BER control register controls Backplane and Local port BER testing. It independently enables and disables
transmission and reception. It is configured as follows:
Bit
Name
Reset
Description
15-7
Unused
0
Set LOW.
6-4
BBPD(2:0)
0
Backplane Block Programming Data.
These bits refer to the value loaded into the Backplane Connection Memory
(BCM) when the Memory Block Programming feature is activated. When the
MBP bit in the Control Register (CR) is set HIGH and the BPE is set HIGH, the
contents of Bits BBPD2-0 are loaded into Bits 15-13, respectively, of the BCM.
Bits 12-0 of the BCM are set LOW.
3-1
LBPD(2:0)
0
Local block Programming Data.
These bits refer to the value loaded into the Local Connection Memory (LCM),
when the Memory Block Programming feature is activated. When the MBP bit in
the Control Register is set HIGH and the BPE is set HIGH, the contents of Bits
LBPD2-0 are loaded into Bits 15-13, respectively, of the LCM.
Bits 12-0 of the LCM are set LOW.
0
BPE
0
Block Programming Enable.
A LOW to HIGH transition of this bit enables the Memory Block Programming
function. A LOW will be returned after 125 us, upon completion of programming.
Set LOW to abort the programming operation.
Table 17 - Block Programming Register Bits
Bit
Name
RESET
Description
15-12
Reserved
0
Reserved.
11
LOCKB
0
Backplane Lock (READ ONLY).
This bit is automatically set HIGH when the receiver has locked to the
incoming data sequence. The bit is reset by a LOW to HIGH transition on
SBERRXB.
10
PRSTB
0
PBER Reset for Backplane.
A LOW to HIGH transition initializes the Backplane BER generator to the
seed value.
9
CBERB
0
Clear Bit Error Rate Register for Backplane.
A LOW to HIGH transition in this bit resets the Backplane internal bit error
counter and the Backplane bit error (BBERR) register to zero.
Table 18 - Bit Error Rate Test Control Register (BERCR) Bits
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90871AV | Flexible 8K Digital Switch (F8KDX) |
| MT90871 | Flexible 8K Digital Switch (F8KDX) |
| MT90883 | TDM to Packet Processors |
| MT91600 | Programmable SLIC |
| MT91600AN | Programmable SLIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90870AG | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 12K X 12K/8K X 4K 1.8V/3.3V 272BGA - Trays |
| MT90870AG2 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 12K X 12K/8K X 4K 1.8V/3.3V 272BGA - Trays |
| MT90871 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Flexible 8K Digital Switch (F8KDX) |
| MT90871AV | 制造商:Microsemi Corporation 功能描述:FLEXIBLE 8K DIGITAL SWITCH 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F8KDX 196PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F8KDX 196PBGA |
| MT90871AV2 | 制造商:Microsemi Corporation 功能描述:PB FREE FLEXIBLE 8K DIGITAL SWITCH - Bulk 制造商:Microsemi Corporation 功能描述:IC, TDM SWITCH 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F8KDX 196PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F8KDX 196PBGA |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。