參數(shù)資料
型號： MT90870
廠商： Zarlink Semiconductor Inc.
英文描述： Flexible 12 k Digital Switch (F12kDX)
中文描述： 靈活的12畝數(shù)字交換機（F12kDX）
文件頁數(shù)： 28/86頁
文件大小： 2093K
代理商： MT90870
MT90870
Data Sheet
28
Zarlink Semiconductor Inc.
approximately 0ns, -15 ns, -30 ns or -45 ns as shown in Figure 12. For 32 Mb/s streams, the advancement may be
0, -1 cycle, -2 cycles or -3 cycles, which converts to approximately 0ns, -7 ns, -15 ns or -22 ns.
Figure 12 - Backplane and Local Output Advancement Timing diagram for Data Rate of 16 Mb/s
4.0 Port High Impedance Control
4.1 Local Port High Impedance Control
The input pin,
LORS
, selects whether the Local output streams,
LSTo0-15
are set to high impedance at the output
of the MT90870 itself, or are always driven (active HIGH or active LOW) and a high impedance state, if required on
a per-channel basis, is invoked through an external interface circuit controlled by the
LCSTo0-1
signals. Setting
LORS
to a LOW state will configure the output streams,
LSTo0-15,
to transmit bi-state channel data with per-
channel high-impedance determined by external circuits under the control of the
LCSTo0-1
outputs. Setting
LORS
to a HIGH state will configure the output streams,
LSTo0-15,
of the MT90870 to invoke a high-impedance output on
a per-channel basis.
The
LORS
pin is an asynchronous input and is expected
to be hard-wired for a particular system application,
although it may be driven under logic control if preferred.
4.1.1 LORS Set LOW
The data (channel control bit) transmitted by
LCSTo0-1
replicates the Local Output Enable Bit (
LE
) of the Local
Connection Memory, with a LOW state indicating the channel to be set to High Impedance. See Section 12.3, Local
Connection Memory Bit Definition for setting the Local Output Enable Bit (
LE
).
The
LCSTo0-1
outputs transmit serial data (channel control bits) at 16.384 Mb/s, with each bit representing the per-
channel high impedance state for specific streams. Eight output streams are allocated to each control line as
follows:
(See also
Pin Description
)
LCSTo0 outputs the channel control bits for streams: LSTo0, 2, 4, 6, 8, 10, 12, and 14.
LCSTo1 outputs the channel control bits for streams: LSTo1, 3, 5, 7, 9, 11, 13, and 15.
The Channel Control Bit location, within a frame period, for each channel of the Local output streams is presented
in
Table 2, LCSTo Allocation of Channel Control Bits to the Output Streams.
Bit Advancement, -2
Bit Advancement, -4
Bit Advancement, -6
FP8o
System Clock
131.072 Mhz
BSTo0-31
/LSTo0-15
Bit Advancement = 0
BSTo0-31
/LSTo0-15
Bit Advancement = -2
(Default)
Bit Advancement = -6
BSTo0-31
/LSTo0-15
Bit Advancement = -4
BSTo0-31
/LSTo0-15
Ch255
Ch255
Ch255
Ch255
Ch0
Ch0
Ch0
Ch0
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 4
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90870AG 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 12K X 12K/8K X 4K 1.8V/3.3V 272BGA - Trays
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MT90871AV 制造商:Microsemi Corporation 功能描述:FLEXIBLE 8K DIGITAL SWITCH 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F8KDX 196PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F8KDX 196PBGA
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