Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
85
Power Supplies for ORT42G5 AND ORT82G5
Power Supply Descriptions
Table shows the ORT42G5 and ORT82G5 FPGA and embedded core power supply groupings. VDD33 Is a 3.3V
positive power supply used for 3.3V conguration RAMs and internal PLLs. When using PLLs, this power supply
should be well isolated from all other power supplies on the board for proper operation. The ve VDDIO supplies
are positive power supply used by the FPGA I/O banks.The 1.5 volt digital power supplies are used for the FPGA
and the embedded core transmit and receive digital logic including the microprocessor logic. The 1.5 volt analog
power supply is used for high-speed analog circuitry in the embedded core between the I/O buffers and the digital
logic. The RX input buffer power supplies are used to power the input (receive) buffers. The TX output buffer sup-
plies are used to power the output (transmit) buffers. The Rx and TX buffer power supplies can be independently
set to 1.5V or 1.8V, depending on the end application. The guard band supplies are independent connection
brought out to pins.
Table 42. Power Supplies
Recommended Power Supply Connections
Ideally, a board should have the power supplies described below:
VDD33 and VDDIO supplies for the FPGA Logic
A single 1.5V source to supply power to FPGA and core digital logic.
A dedicated 1.5V power supply for the analog power pins. This will allow the end user to minimize noise. The
guard band pins can also be sourced from the analog power supplies.
TX output buffer power. The power supplies to the TS output buffers should be isolated from the rest of the board
power supplies. Special care must be taken to minimize noise when providing board level power to these output
buffers. The power supply can be 1.5V or 1.8V depending on the end application.
RX input buffer power. The power supplies to the Rx input buffers should be isolated from the rest of the board
power supplies. Special care must be taken to minimize noise when providing board level power to these input
buffers. The power supply can be 1.5V or 1.8V depending on the end application.
Recommended Power Supply Filtering Scheme
The board connections of the various SERDES VDD and VSS pins are critical to system performance. An example
demonstration board schematic is available at www.latticesemi.com.
Power supply ltering is in the form of:
A parallel bypass capacitor network consisting of 10 f, 0.1 f, and 1.0 f caps close to the power source.
A parallel bypass capacitor network consisting of 0.01 f and 0.1 f close to the pin on the ORT42G5.
FPGA Supplies
FPGA and Core
Digital Supply
1.5V
Analog 1.5V
Tx Output Buffers
1.5V/1.8V
(VDDOB)
Rx Input Buffers
1.5V/1.8V
(VDDIB)
Guard Band
1.5V
(VDDGB)
VDD33
VDD15
VDD_ANA
VDDOB_AA
1
VDDIB_AA
1
VDDGB_A
VDDIO0
—
VDDOB_AB
1
VDDIB_AB
1
VDDGB_B
VDDIO1
—
VDDOB_AC
VDDIB_AC
—
VDDIO5
—
VDDOB_AD
VDDIB_AD
—
VDDIO6
—
VDDOB_BA
1
VDDIB_BA
1
—
VDDIO7
—
VDDOB_BB
1
VDDIB_BB
1
—
VDDOB_BC
VDDIB_BC
—
VDDOB_BD
VDDIB_BD
—
1. ORT82G5 only.