參數(shù)資料
型號： ORT82G5-3FN680C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 89/119頁
文件大小： 0K
描述： IC TRANCEIVERS FPSC 680FPBGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
71
30810 - Ax
30910 - Bx
[0]xA
[1]xB
[2]xC
[3]xD
DOWDALIGN_xx
00
Word Realign Bit. When DOWDALIGN_xx transitions from 0 to 1, the
receiver realigns on the next comma character for Channel xx.
NOWDALIGN_xx=0 on device reset.
[4]xA
[5]xB
[6]xC
[7]xD
FMPU_STR_EN
_xx
Enable multi-channel alignment for Channel xx. When
FMPU_STR_EN_xx=1, the corresponding channel participates in multi-
channel alignment. FMPU_STR_EN_xx=0 on device reset.
30811 - Ax
30911 - Bx
[0:1]
xA
[2:3]
xB
[4:5]
xC
[6:7]
xD
FMPU_SYNMOD
E_xx[0:1]
00
Sync mode for xx
00 = No channel alignment
10 = Twin channel alignment
01 = Quad channel alignment
11 = Eight channel alignment
30820 - Ax
30920 - Bx
[0]xA
[1]xB
[2]xC
[3]xD
FMPU_RESYNC1
_xx
00
Resync a Single Channel. When FMPU_RESYNC1_xx transitions from
0 to 1, the corresponding channel is resynchronized (the write and read
pointers are reset). FMPU_STR_EN_xx=0 on device reset.
[4]
xA & xB
[5] xC & xD
FMPU_RESYNC2
_x[1:2]
Resync a Pair of Channels. When FMPU_RESYNC2_[A:B][1:2] transi-
tions from a 0 to a 1, the corresponding channel pair is resynchronized.
FFMPU_RESYNC2_[A:B][1:2]=0 on device reset.
[6]
FMPU_RESYNC4
[A:B]
Resync a Four-Channel Group. When FMPU_RESYNC4[A:B] transitions
from a 0 to a 1, the corresponding four-channel group is resynchronized.
FMPU_RESYNC4[A:B]=0 on device reset.
[7]
XAUI_MODE[A:B]
Controls use of XAUI link state machine in place of Fibre-Channel state
machine. When XAUI_MODE[A:B]=1, all four channels in the SERDES
quad enable their XAUI link state machines. (LINKSM_xx bits are
ignored). XAUI_MODE[A:B]=0 on device reset.
30821 - A
30921 - B
[0]
NOCHALGN [A:B]
00
Bypass channel alignment. NOCHALGN [A:B] =1 causes bypassing of
multi-channel alignment FIFOs for the corresponding SERDES quad.
NOCHALGN [A:B] =0 on device reset.
[1:7]
Reserved for future use.
30933
[0:3]
Reserved for future use.
[4:5]
SCHAR_CHAN[0:
1]
00
Select channel to test
00 = Channel BA
10 = Channel BB
01 =Channel BC
11 = Channel BD
[6]
SCHAR_TXSEL
1=Select TX option
0=Select RX option
[7]
SCHAR_ENA
1=Enable Characterization of SERDES B
Status Registers (Read Only), xx=[AA,...,BD]
30804 - Ax
30904 - Bx
[0:1]
xA
[2:3]
xB
[4:5]
xC
[6:7]
xD
XAUISTAT_xx[0:1]
00
XAUI Status Register. Status of XAUI link state machine for Channel xx
00 – No synchronization.
10 – Synchronization done.
11 – Not used.
01 – no_comma (see XAUI state machine) and at least one CV detected
XAUISTAT_xx[0:1] = 00 on device reset.
Table 30. ORT82G5 Memory Map (Continued)
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
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ORT82G5-3FN680C1 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-FPSC-EV 功能描述:可編程邏輯 IC 開發(fā)工具 Ev Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓:
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ORT8850-FPSC-EV 功能描述:可編程邏輯 IC 開發(fā)工具 ORCA ORT8850 FPSC Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓:
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